test: update.
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@ -68,7 +68,7 @@ class _CRG(Module):
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, toolchain, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, **kwargs):
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def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, **kwargs):
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platform = arty.Platform(toolchain=toolchain)
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# SoCCore ----------------------------------------------------------------------------------
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@ -74,9 +74,9 @@ class TestTargets(unittest.TestCase):
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self.assertEqual(errors, 0)
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def test_arty_symbiflow(self):
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from litex.boards.targets.arty_symbiflow import BaseSoC
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from litex.boards.targets.arty import BaseSoC
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errors = build_test([
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BaseSoC(**test_kwargs)
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BaseSoC(toolchain="symbiflow", **test_kwargs)
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])
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self.assertEqual(errors, 0)
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