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clock/efinix_trion: Cleanup PLL block, fix reset polarity and always enable it.

This commit is contained in:
Florent Kermarrec 2021-10-25 17:49:39 +02:00
parent 36b26006a4
commit 5dc377eda1
2 changed files with 12 additions and 19 deletions
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4
litex/build/efinix/ifacewriter.py
View File

@ -328,8 +328,8 @@ design.create('{2}', '{3}', './../gateware', overwrite=True)
cmd += 'design.set_property("{}", "CORE_CLK_PIN", "{}", block_type="PLL")\n\n'.format(name, block['input_signal'])
cmd += 'design.set_property("{}","LOCKED_PIN","{}", block_type="PLL")\n'.format(name, block['locked'])
if block['reset'] != '':
cmd += 'design.set_property("{}","RSTN_PIN","{}", block_type="PLL")\n\n'.format(name, block['reset'])
if block['rstn'] != '':
cmd += 'design.set_property("{}","RSTN_PIN","{}", block_type="PLL")\n\n'.format(name, block['rstn'])
# Output clock 0 is enabled by default
for i, clock in enumerate(block['clk_out']):

27
litex/soc/cores/clock/efinix_trion.py
View File

@ -17,7 +17,7 @@ class Open(Signal): pass
class TRIONPLL(Module):
nclkouts_max = 4
def __init__(self, platform, with_reset=False):
def __init__(self, platform):
self.logger = logging.getLogger("TRIONPLL")
self.logger.info("Creating TRIONPLL.".format())
self.platform = platform
@ -26,26 +26,19 @@ class TRIONPLL(Module):
self.reset = Signal()
self.locked = Signal()
# Create PLL block.
block = {}
block["type"] = "PLL"
block["name"] = self.pll_name
block["type"] = "PLL"
block["name"] = self.pll_name
block["clk_out"] = []
pll_locked_name = self.pll_name + "_locked"
block["locked"] = pll_locked_name
io = self.platform.add_iface_io(pll_locked_name)
self.comb += self.locked.eq(io)
block["reset"] = ""
if with_reset:
pll_reset_name = self.pll_name + "_reset"
block["reset"] = pll_reset_name
io = self.platform.add_iface_io(pll_reset_name)
self.comb += io.eq(self.reset)
block["locked"] = self.pll_name + "_locked"
block["rstn"] = self.pll_name + "_rstn"
self.platform.toolchain.ifacewriter.blocks.append(block)
# Connect PLL's rstn/locked.
self.comb += self.platform.add_iface_io(self.pll_name + "_rstn").eq(~self.reset)
self.comb += self.locked.eq(self.platform.add_iface_io(self.pll_name + "_locked"))
def register_clkin(self, clkin, freq, name= ""):
block = self.platform.toolchain.ifacewriter.get_block(self.pll_name)