clock/efinix_trion: Cleanup PLL block, fix reset polarity and always enable it.
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36b26006a4
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5dc377eda1
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@ -328,8 +328,8 @@ design.create('{2}', '{3}', './../gateware', overwrite=True)
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cmd += 'design.set_property("{}", "CORE_CLK_PIN", "{}", block_type="PLL")\n\n'.format(name, block['input_signal'])
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cmd += 'design.set_property("{}","LOCKED_PIN","{}", block_type="PLL")\n'.format(name, block['locked'])
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if block['reset'] != '':
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cmd += 'design.set_property("{}","RSTN_PIN","{}", block_type="PLL")\n\n'.format(name, block['reset'])
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if block['rstn'] != '':
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cmd += 'design.set_property("{}","RSTN_PIN","{}", block_type="PLL")\n\n'.format(name, block['rstn'])
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# Output clock 0 is enabled by default
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for i, clock in enumerate(block['clk_out']):
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@ -17,7 +17,7 @@ class Open(Signal): pass
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class TRIONPLL(Module):
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nclkouts_max = 4
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def __init__(self, platform, with_reset=False):
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def __init__(self, platform):
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self.logger = logging.getLogger("TRIONPLL")
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self.logger.info("Creating TRIONPLL.".format())
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self.platform = platform
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@ -26,26 +26,19 @@ class TRIONPLL(Module):
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self.reset = Signal()
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self.locked = Signal()
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# Create PLL block.
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block = {}
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block["type"] = "PLL"
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block["name"] = self.pll_name
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block["type"] = "PLL"
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block["name"] = self.pll_name
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block["clk_out"] = []
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pll_locked_name = self.pll_name + "_locked"
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block["locked"] = pll_locked_name
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io = self.platform.add_iface_io(pll_locked_name)
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self.comb += self.locked.eq(io)
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block["reset"] = ""
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if with_reset:
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pll_reset_name = self.pll_name + "_reset"
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block["reset"] = pll_reset_name
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io = self.platform.add_iface_io(pll_reset_name)
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self.comb += io.eq(self.reset)
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block["locked"] = self.pll_name + "_locked"
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block["rstn"] = self.pll_name + "_rstn"
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self.platform.toolchain.ifacewriter.blocks.append(block)
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# Connect PLL's rstn/locked.
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self.comb += self.platform.add_iface_io(self.pll_name + "_rstn").eq(~self.reset)
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self.comb += self.locked.eq(self.platform.add_iface_io(self.pll_name + "_locked"))
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def register_clkin(self, clkin, freq, name= ""):
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block = self.platform.toolchain.ifacewriter.get_block(self.pll_name)
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