Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

bios: we can now use -Ot with_rom True on targets to force bios implementation in integrated rom (can speed up debug we don't want to reflash SPI or NOR flash)

This commit is contained in:
Florent Kermarrec 2015-02-27 17:22:44 +01:00
parent b031c5edae
commit 5e2e9338d2
4 changed files with 26 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
targets/kc705.py
View File

@ -98,15 +98,16 @@ class BaseSoC(SDRAMSoC):
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
self.register_sdram_phy(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing)
# BIOS is in SPI flash
spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
self.flash_boot_address = 0xb00000
self.register_rom(self.spiflash.bus)
# If not in ROM, BIOS is in SPI flash
if not self.with_rom:
spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
self.flash_boot_address = 0xb00000
self.register_rom(self.spiflash.bus)
class MiniSoC(BaseSoC):
csr_map = {

10
targets/mlabs_video.py
View File

@ -54,10 +54,12 @@ class BaseSoC(SDRAMSoC):
rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
self.register_sdram_phy(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing)
self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
self.ns(110), self.ns(50))
self.flash_boot_address = 0x001a0000
self.register_rom(self.norflash.bus)
# If not in ROM, BIOS is in // NOR flash
if not self.with_rom:
self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
self.ns(110), self.ns(50))
self.flash_boot_address = 0x001a0000
self.register_rom(self.norflash.bus)
self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
self.comb += [

9
targets/pipistrello.py
View File

@ -97,9 +97,10 @@ class BaseSoC(SDRAMSoC):
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
self.register_sdram_phy(self.sdrphy.dfi, self.sdrphy.phy_settings, sdram_geom, sdram_timing)
# BIOS is in SPI flash
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
self.flash_boot_address = 0x70000
self.register_rom(self.spiflash.bus)
# If not in ROM, BIOS is in SPI flash
if not self.with_rom:
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
self.flash_boot_address = 0x70000
self.register_rom(self.spiflash.bus)
default_subtarget = BaseSoC

9
targets/ppro.py
View File

@ -91,9 +91,10 @@ class BaseSoC(SDRAMSoC):
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
self.register_sdram_phy(self.sdrphy.dfi, self.sdrphy.phy_settings, sdram_geom, sdram_timing)
# BIOS is in SPI flash
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
self.flash_boot_address = 0x70000
self.register_rom(self.spiflash.bus)
# If not in ROM, BIOS is in SPI flash
if not self.with_rom:
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
self.flash_boot_address = 0x70000
self.register_rom(self.spiflash.bus)
default_subtarget = BaseSoC