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soc/add_pcie: Automatically set Endpoint's endianness to PHY's endianness.

This commit is contained in:
Florent Kermarrec 2021-10-12 15:38:39 +02:00
parent f93b6b9f27
commit 5e3e78f760
1 changed files with 1 additions and 1 deletions
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2
litex/soc/integration/soc.py
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@ -1695,7 +1695,7 @@ class LiteXSoC(SoC):
# Endpoint. # Endpoint.
self.check_if_exists(f"{name}_endpoint") self.check_if_exists(f"{name}_endpoint")
endpoint = LitePCIeEndpoint(phy, max_pending_requests=max_pending_requests) endpoint = LitePCIeEndpoint(phy, max_pending_requests=max_pending_requests, endianness=phy.endianness)
setattr(self.submodules, f"{name}_endpoint", endpoint) setattr(self.submodules, f"{name}_endpoint", endpoint)
# MMAP. # MMAP.