Merge pull request #1277 from trabucayre/uart_fix_Stream2Wishbone_v2
Uart fix stream2 wishbone v2
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commit
5e451d68f7
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@ -312,17 +312,17 @@ class Stream2Wishbone(Module):
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# # #
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# # #
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assert data_width == address_width
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cmd = Signal(8, reset_less=True)
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incr = Signal()
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length = Signal(8, reset_less=True)
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address = Signal(address_width, reset_less=True)
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data = Signal(data_width, reset_less=True)
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data_bytes_count = Signal(int(log2(data_width//8)), reset_less=True)
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addr_bytes_count = Signal(int(log2(address_width//8)), reset_less=True)
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words_count = Signal(8, reset_less=True)
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cmd = Signal(8, reset_less=True)
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data_bytes_count_done = (data_bytes_count == (data_width//8 - 1))
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incr = Signal()
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addr_bytes_count_done = (addr_bytes_count == (address_width//8 - 1))
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length = Signal(8, reset_less=True)
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address = Signal(address_width, reset_less=True)
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data = Signal(data_width, reset_less=True)
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bytes_count = Signal(int(log2(data_width//8)), reset_less=True)
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words_count = Signal(8, reset_less=True)
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bytes_count_done = (bytes_count == (data_width//8 - 1))
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words_count_done = (words_count == (length - 1))
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words_count_done = (words_count == (length - 1))
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self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="RECEIVE-CMD"))
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self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="RECEIVE-CMD"))
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@ -331,7 +331,8 @@ class Stream2Wishbone(Module):
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self.comb += fsm.reset.eq(timer.done)
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self.comb += fsm.reset.eq(timer.done)
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fsm.act("RECEIVE-CMD",
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fsm.act("RECEIVE-CMD",
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sink.ready.eq(1),
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sink.ready.eq(1),
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NextValue(bytes_count, 0),
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NextValue(data_bytes_count, 0),
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NextValue(addr_bytes_count, 0),
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NextValue(words_count, 0),
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NextValue(words_count, 0),
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If(sink.valid,
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If(sink.valid,
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NextValue(cmd, sink.data),
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NextValue(cmd, sink.data),
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@ -349,8 +350,8 @@ class Stream2Wishbone(Module):
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sink.ready.eq(1),
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sink.ready.eq(1),
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If(sink.valid,
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If(sink.valid,
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NextValue(address, Cat(sink.data, address)),
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NextValue(address, Cat(sink.data, address)),
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NextValue(bytes_count, bytes_count + 1),
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NextValue(addr_bytes_count, addr_bytes_count + 1),
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If(bytes_count_done,
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If(addr_bytes_count_done,
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If((cmd == CMD_WRITE_BURST_INCR) | (cmd == CMD_WRITE_BURST_FIXED),
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If((cmd == CMD_WRITE_BURST_INCR) | (cmd == CMD_WRITE_BURST_FIXED),
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NextValue(incr, cmd == CMD_WRITE_BURST_INCR),
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NextValue(incr, cmd == CMD_WRITE_BURST_INCR),
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NextState("RECEIVE-DATA")
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NextState("RECEIVE-DATA")
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@ -367,8 +368,8 @@ class Stream2Wishbone(Module):
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sink.ready.eq(1),
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sink.ready.eq(1),
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If(sink.valid,
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If(sink.valid,
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NextValue(data, Cat(sink.data, data)),
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NextValue(data, Cat(sink.data, data)),
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NextValue(bytes_count, bytes_count + 1),
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NextValue(data_bytes_count, data_bytes_count + 1),
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If(bytes_count_done,
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If(data_bytes_count_done,
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NextState("WRITE-DATA")
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NextState("WRITE-DATA")
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)
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)
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)
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)
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@ -406,13 +407,13 @@ class Stream2Wishbone(Module):
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cases = {}
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cases = {}
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for i, n in enumerate(reversed(range(data_width//8))):
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for i, n in enumerate(reversed(range(data_width//8))):
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cases[i] = source.data.eq(data[8*n:])
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cases[i] = source.data.eq(data[8*n:])
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self.comb += Case(bytes_count, cases)
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self.comb += Case(data_bytes_count, cases)
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fsm.act("SEND-DATA",
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fsm.act("SEND-DATA",
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sink.ready.eq(0),
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sink.ready.eq(0),
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source.valid.eq(1),
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source.valid.eq(1),
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If(source.ready,
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If(source.ready,
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NextValue(bytes_count, bytes_count + 1),
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NextValue(data_bytes_count, data_bytes_count + 1),
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If(bytes_count_done,
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If(data_bytes_count_done,
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NextValue(words_count, words_count + 1),
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NextValue(words_count, words_count + 1),
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NextValue(address, address + incr),
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NextValue(address, address + incr),
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If(words_count_done,
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If(words_count_done,
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@ -423,7 +424,7 @@ class Stream2Wishbone(Module):
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)
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)
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)
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)
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)
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)
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self.comb += source.last.eq(bytes_count_done & words_count_done)
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self.comb += source.last.eq(data_bytes_count_done & words_count_done)
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if hasattr(source, "length"):
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if hasattr(source, "length"):
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self.comb += source.length.eq((data_width//8)*length)
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self.comb += source.length.eq((data_width//8)*length)
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