Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

soc/cores/uart:Stream2Wishbone: remove no more needed data_width/address_width equality test

Browse source
This commit is contained in:
Gwenhael Goavec-Merou 2022-04-15 17:43:50 +02:00
parent 3cb34e7951
commit a988712974
1 changed files with 0 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
litex/soc/cores/uart.py
View file

@ -312,8 +312,6 @@ class Stream2Wishbone(Module):
# # #
assert data_width == address_width
cmd = Signal(8, reset_less=True)
incr = Signal()
length = Signal(8, reset_less=True)