soc/cores/uart:Stream2Wishbone: remove no more needed data_width/address_width equality test

2022-04-15 17:43:50 +02:00 · 2022-04-15 17:43:50 +02:00 · a988712974
parent 3cb34e7951
commit a988712974
1 changed files with 0 additions and 2 deletions
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@ -312,8 +312,6 @@ class Stream2Wishbone(Module):

        # # #

-        assert data_width == address_width
-
        cmd              = Signal(8,                           reset_less=True)
        incr             = Signal()
        length           = Signal(8,                           reset_less=True)