Vivado Command Update for Systemverilog
Add BlackParrot to LiteX setup file
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@ -137,7 +137,9 @@ class XilinxVivadoToolchain:
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for filename, language, library in platform.sources:
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filename_tcl = "{" + filename + "}"
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if (language == "systemverilog"):
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tcl.append("read_verilog -sv " + filename_tcl)
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tcl.append("read_verilog -v " + filename_tcl)
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tcl.append("set_property file_type SystemVerilog [get_files {}]"
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.format(filename_tcl))
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elif (language == "verilog"):
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tcl.append("read_verilog " + filename_tcl)
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elif (language == "vhdl"):
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@ -120,7 +120,7 @@ class BlackParrotRV64(CPU):
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def add_sources(platform, variant="standard"):
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vdir = get_data_mod("cpu", "blackparrot").data_location
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bp_litex_dir = os.path.join(vdir,"bp_litex")
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simulation = 1
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simulation = 0
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if (simulation == 1):
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filename= os.path.join(bp_litex_dir,"flist.verilator")
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else:
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@ -144,7 +144,7 @@ class BlackParrotRV64(CPU):
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a = os.popen('echo '+ str(dir_))
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dir_start = a.read()
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vdir = dir_start[:-1]+ line[s2:-1]
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platform.add_source(vdir) #this line might be changed
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platform.add_source(vdir, "systemverilog") #this line might be changed
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elif (temp[0] == '/'):
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assert("No support for absolute path for now")
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@ -48,6 +48,7 @@ repos = [
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("pythondata-cpu-rocket", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-minerva", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-microwatt", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-blackparrot", ("https://github.com/litex-hub/", False, True)),
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]
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repos = OrderedDict(repos)
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