Vivado Command Update for Systemverilog

Add BlackParrot to LiteX setup file
This commit is contained in:
sadullah 2020-05-08 02:17:37 -04:00
parent 3ce9010083
commit 5e4a436089
3 changed files with 6 additions and 3 deletions

View File

@ -137,7 +137,9 @@ class XilinxVivadoToolchain:
for filename, language, library in platform.sources:
filename_tcl = "{" + filename + "}"
if (language == "systemverilog"):
tcl.append("read_verilog -sv " + filename_tcl)
tcl.append("read_verilog -v " + filename_tcl)
tcl.append("set_property file_type SystemVerilog [get_files {}]"
.format(filename_tcl))
elif (language == "verilog"):
tcl.append("read_verilog " + filename_tcl)
elif (language == "vhdl"):

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@ -120,7 +120,7 @@ class BlackParrotRV64(CPU):
def add_sources(platform, variant="standard"):
vdir = get_data_mod("cpu", "blackparrot").data_location
bp_litex_dir = os.path.join(vdir,"bp_litex")
simulation = 1
simulation = 0
if (simulation == 1):
filename= os.path.join(bp_litex_dir,"flist.verilator")
else:
@ -144,7 +144,7 @@ class BlackParrotRV64(CPU):
a = os.popen('echo '+ str(dir_))
dir_start = a.read()
vdir = dir_start[:-1]+ line[s2:-1]
platform.add_source(vdir) #this line might be changed
platform.add_source(vdir, "systemverilog") #this line might be changed
elif (temp[0] == '/'):
assert("No support for absolute path for now")

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@ -48,6 +48,7 @@ repos = [
("pythondata-cpu-rocket", ("https://github.com/litex-hub/", False, True)),
("pythondata-cpu-minerva", ("https://github.com/litex-hub/", False, True)),
("pythondata-cpu-microwatt", ("https://github.com/litex-hub/", False, True)),
("pythondata-cpu-blackparrot", ("https://github.com/litex-hub/", False, True)),
]
repos = OrderedDict(repos)