tools/litex_json2dts: cleanup and reorganize peripherals.
This commit is contained in:
Florent Kermarrec
parent
df92e2aea7
commit
5ec5554713
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@ -21,8 +21,7 @@ def generate_dts(d):
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aliases = {}
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# Header -------------------------------------------------------------------------------------------
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# Header ---------------------------------------------------------------------------------------
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dts = """
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/dts-v1/;
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@ -32,8 +31,7 @@ def generate_dts(d):
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"""
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# Boot Arguments -----------------------------------------------------------------------------------
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# Boot Arguments -------------------------------------------------------------------------------
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linux_initrd_start_offset = {
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"mor1kx": 8*mB,
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"vexriscv smp-linux" : 16*mB,
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@ -49,14 +47,16 @@ def generate_dts(d):
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linux,initrd-start = <0x{linux_initrd_start:x}>;
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linux,initrd-end = <0x{linux_initrd_end:x}>;
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}};
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""".format(main_ram_base=d["memories"]["main_ram"]["base"],
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main_ram_size=d["memories"]["main_ram"]["size"],
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main_ram_size_mb=d["memories"]["main_ram"]["size"] // mB,
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linux_initrd_start=d["memories"]["main_ram"]["base"] + linux_initrd_start_offset[cpu_name],
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linux_initrd_end=d["memories"]["main_ram"]["base"] + linux_initrd_end_offset[cpu_name])
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""".format(
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main_ram_base = d["memories"]["main_ram"]["base"],
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main_ram_size = d["memories"]["main_ram"]["size"],
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main_ram_size_mb = d["memories"]["main_ram"]["size"] // mB,
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linux_initrd_start = d["memories"]["main_ram"]["base"] + linux_initrd_start_offset[cpu_name],
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linux_initrd_end = d["memories"]["main_ram"]["base"] + linux_initrd_end_offset[cpu_name])
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# CPU ----------------------------------------------------------------------------------------------
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# CPU ------------------------------------------------------------------------------------------
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# VexRiscv-SMP
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if cpu_name == "vexriscv smp-linux":
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dts += """
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cpus {{
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@ -64,7 +64,6 @@ def generate_dts(d):
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#size-cells = <0>;
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timebase-frequency = <{sys_clk_freq}>;
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""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
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cpus = range(int(d["constants"]["config_cpu_count"]))
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for cpu in cpus:
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dts += """
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@ -82,13 +81,12 @@ def generate_dts(d):
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}};
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}};
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""".format(cpu=cpu, irq=cpu)
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dts += """
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};
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"""
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# mor1kx
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elif cpu_name == "mor1kx":
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dts += """
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cpus {{
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#address-cells = <1>;
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@ -101,19 +99,19 @@ def generate_dts(d):
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}};
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""".format(sys_clk_freq=d["constants"]["config_clock_frequency"])
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# Memory -------------------------------------------------------------------------------------------
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# Memory ---------------------------------------------------------------------------------------
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dts += """
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memory@{main_ram_base:x} {{
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device_type = "memory";
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reg = <0x{main_ram_base:x} 0x{main_ram_size:x}>;
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}};
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""".format(main_ram_base=d["memories"]["main_ram"]["base"],
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main_ram_size=d["memories"]["main_ram"]["size"])
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""".format(
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main_ram_base = d["memories"]["main_ram"]["base"],
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main_ram_size = d["memories"]["main_ram"]["size"])
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if "opensbi" in d["memories"]:
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dts += """
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reserved-memory {{
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#address-cells = <1>;
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#size-cells = <1>;
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@ -122,10 +120,11 @@ def generate_dts(d):
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reg = <0x{opensbi_base:x} 0x{opensbi_size:x}>;
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}};
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}};
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""".format(opensbi_base=d["memories"]["opensbi"]["base"],
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opensbi_size=d["memories"]["opensbi"]["size"])
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""".format(
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opensbi_base = d["memories"]["opensbi"]["base"],
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opensbi_size = d["memories"]["opensbi"]["size"])
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# SoC ----------------------------------------------------------------------------------------------
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# SoC ------------------------------------------------------------------------------------------
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dts += """
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soc {{
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@ -136,11 +135,21 @@ def generate_dts(d):
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ranges;
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""".format(sys_clk_freq=d["constants"]["config_clock_frequency"])
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# Interrupt controller -----------------------------------------------------------------------------
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# SoC Controller -------------------------------------------------------------------------------
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dts += """
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soc_ctrl0: soc_controller@{soc_ctrl_csr_base:x} {{
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compatible = "litex,soc_controller";
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reg = <0x{soc_ctrl_csr_base:x} 0xc>;
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status = "okay";
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}};
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""".format(soc_ctrl_csr_base=d["csr_bases"]["ctrl"])
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# Interrupt Controller -------------------------------------------------------------------------
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if cpu_name == "vexriscv smp-linux":
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dts += """
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plic: interrupt-controller@{plic_base:x} {{
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intc0: interrupt-controller@{plic_base:x} {{
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compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic";
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reg = <0x{plic_base:x} 0x400000>;
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#interrupt-cells = <1>;
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@ -149,8 +158,9 @@ def generate_dts(d):
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{cpu_mapping}>;
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riscv,ndev = <32>;
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}};
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""".format( plic_base=d["memories"]["plic"]["base"],
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cpu_mapping="\n\t\t\t\t".join(["&L{} 11 &L{} 9".format(cpu, cpu) for cpu in cpus]))
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""".format(
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plic_base =d["memories"]["plic"]["base"],
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cpu_mapping =("\n" + " "*20).join(["&L{} 11 &L{} 9".format(cpu, cpu) for cpu in cpus]))
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elif cpu_name == "mor1kx":
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dts += """
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@ -161,27 +171,10 @@ def generate_dts(d):
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status = "okay";
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};
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"""
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else:
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raise Exception("Unsupported CPU type: {}".format(cpu_name))
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# SoC Controller -----------------------------------------------------------------------------------
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dts += """
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soc_ctrl0: soc_controller@{soc_ctrl_csr_base:x} {{
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compatible = "litex,soc_controller";
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reg = <0x{soc_ctrl_csr_base:x} 0xc>;
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status = "okay";
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}};
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""".format(soc_ctrl_csr_base=d["csr_bases"]["ctrl"])
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# UART ---------------------------------------------------------------------------------------------
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# UART -----------------------------------------------------------------------------------------
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if "uart" in d["csr_bases"]:
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aliases["serial0"] = "liteuart0"
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dts += """
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liteuart0: serial@{uart_csr_base:x} {{
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device_type = "serial";
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@ -191,10 +184,9 @@ def generate_dts(d):
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}};
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""".format(uart_csr_base=d["csr_bases"]["uart"])
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# Ethernet MAC -------------------------------------------------------------------------------------
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# Ethernet -------------------------------------------------------------------------------------
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if "ethphy" in d["csr_bases"] and "ethmac" in d["csr_bases"]:
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dts += """
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mac0: mac@{ethmac_csr_base:x} {{
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compatible = "litex,liteeth";
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@ -204,88 +196,17 @@ def generate_dts(d):
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tx-fifo-depth = <{ethmac_tx_slots}>;
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rx-fifo-depth = <{ethmac_rx_slots}>;
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}};
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""".format(ethphy_csr_base=d["csr_bases"]["ethphy"],
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ethmac_csr_base=d["csr_bases"]["ethmac"],
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ethmac_mem_base=d["memories"]["ethmac"]["base"],
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ethmac_tx_slots=d["constants"]["ethmac_tx_slots"],
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ethmac_rx_slots=d["constants"]["ethmac_rx_slots"])
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""".format(
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ethphy_csr_base = d["csr_bases"]["ethphy"],
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ethmac_csr_base = d["csr_bases"]["ethmac"],
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ethmac_mem_base = d["memories"]["ethmac"]["base"],
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ethmac_tx_slots = d["constants"]["ethmac_tx_slots"],
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ethmac_rx_slots = d["constants"]["ethmac_rx_slots"])
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# Leds ---------------------------------------------------------------------------------------------
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if "leds" in d["csr_bases"]:
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dts += """
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leds: gpio@{leds_csr_base:x} {{
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compatible = "litex,gpio";
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reg = <0x{leds_csr_base:x} 0x4>;
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litex,direction = "out";
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status = "disabled";
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}};
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""".format(leds_csr_base=d["csr_bases"]["leds"])
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# RGB Led ------------------------------------------------------------------------------------------
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for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
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if name in d["csr_bases"]:
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dts += """
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{pwm_name}: pwm@{pwm_csr_base:x} {{
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compatible = "litex,pwm";
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reg = <0x{pwm_csr_base:x} 0x24>;
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clock = <100000000>;
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#pwm-cells = <3>;
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status = "okay";
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}};
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""".format(pwm_name=name,
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pwm_csr_base=d["csr_bases"][name])
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# Switches -----------------------------------------------------------------------------------------
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if "switches" in d["csr_bases"]:
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dts += """
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switches: gpio@{switches_csr_base:x} {{
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compatible = "litex,gpio";
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reg = <0x{switches_csr_base:x} 0x4>;
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litex,direction = "in";
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status = "disabled";
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}};
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""".format(switches_csr_base=d["csr_bases"]["switches"])
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# SPI ----------------------------------------------------------------------------------------------
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if "spi" in d["csr_bases"]:
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aliases["spi0"] = "litespi0"
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dts += """
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litespi0: spi@{spi_csr_base:x} {{
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compatible = "litex,litespi";
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reg = <0x{spi_csr_base:x} 0x100>;
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status = "okay";
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litespi,max-bpw = <8>;
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litespi,sck-frequency = <1000000>;
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litespi,num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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spidev0: spidev@0 {{
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compatible = "linux,spidev";
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reg = <0>;
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spi-max-frequency = <1000000>;
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status = "okay";
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}};
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}};
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""".format(spi_csr_base=d["csr_bases"]["spi"])
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# SPIFLASH -------------------------------------------------------------------------------------------
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# SPI Flash -------------------------------------------------------------------------------------
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if "spiflash" in d["csr_bases"]:
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aliases["spiflash"] = "litespiflash"
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dts += """
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litespiflash: spiflash@{spiflash_csr_base:x} {{
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#address-cells = <1>;
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@ -297,15 +218,12 @@ def generate_dts(d):
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reg = <0x0 0x{spiflash_size:x}>;
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}};
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}};
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""".format(spiflash_csr_base=d["csr_bases"]["spiflash"],
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spiflash_size=d["memories"]["spiflash"]["size"])
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""".format(spiflash_csr_base=d["csr_bases"]["spiflash"], spiflash_size=d["memories"]["spiflash"]["size"])
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# SPISDCARD ----------------------------------------------------------------------------------------
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# SPI-SDCard -----------------------------------------------------------------------------------
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if "spisdcard" in d["csr_bases"]:
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aliases["sdcard0"] = "litespisdcard0"
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dts += """
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litespisdcard0: spi@{spisdcard_csr_base:x} {{
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compatible = "litex,litespi";
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@ -329,10 +247,95 @@ def generate_dts(d):
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}};
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""".format(spisdcard_csr_base=d["csr_bases"]["spisdcard"])
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# I2C ----------------------------------------------------------------------------------------------
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# SDCard ---------------------------------------------------------------------------------------
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if "sdcore" in d["csr_bases"]:
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dts += """
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mmc0: mmc@{mmc_csr_base:x} {{
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compatible = "litex,mmc";
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reg = <
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0x{sdphy_csr_base:x} 0x100
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0x{sdcore_csr_base:x} 0x100
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0x{sdblock2mem:x} 0x100
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0x{sdmem2block:x} 0x100>;
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bus-width = <0x04>;
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status = "okay";
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}};
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""".format(
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mmc_csr_base = d["csr_bases"]["sdcore"],
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sdphy_csr_base = d["csr_bases"]["sdphy"],
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sdcore_csr_base = d["csr_bases"]["sdcore"],
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sdblock2mem = d["csr_bases"]["sdblock2mem"],
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sdmem2block = d["csr_bases"]["sdmem2block"]
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)
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# Leds -----------------------------------------------------------------------------------------
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if "leds" in d["csr_bases"]:
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dts += """
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leds: gpio@{leds_csr_base:x} {{
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compatible = "litex,gpio";
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reg = <0x{leds_csr_base:x} 0x4>;
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litex,direction = "out";
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status = "disabled";
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}};
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""".format(leds_csr_base=d["csr_bases"]["leds"])
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# RGB Leds -------------------------------------------------------------------------------------
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for name in ["rgb_led_r0", "rgb_led_g0", "rgb_led_b0"]:
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if name in d["csr_bases"]:
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dts += """
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{pwm_name}: pwm@{pwm_csr_base:x} {{
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compatible = "litex,pwm";
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reg = <0x{pwm_csr_base:x} 0x24>;
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clock = <100000000>;
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#pwm-cells = <3>;
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status = "okay";
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}};
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""".format(pwm_name=name, pwm_csr_base=d["csr_bases"][name])
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# Switches -------------------------------------------------------------------------------------
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if "switches" in d["csr_bases"]:
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dts += """
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switches: gpio@{switches_csr_base:x} {{
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compatible = "litex,gpio";
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reg = <0x{switches_csr_base:x} 0x4>;
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litex,direction = "in";
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status = "disabled";
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}};
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""".format(switches_csr_base=d["csr_bases"]["switches"])
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# SPI ------------------------------------------------------------------------------------------
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if "spi" in d["csr_bases"]:
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aliases["spi0"] = "litespi0"
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dts += """
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litespi0: spi@{spi_csr_base:x} {{
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compatible = "litex,litespi";
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reg = <0x{spi_csr_base:x} 0x100>;
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status = "okay";
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litespi,max-bpw = <8>;
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litespi,sck-frequency = <1000000>;
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litespi,num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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spidev0: spidev@0 {{
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compatible = "linux,spidev";
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reg = <0>;
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spi-max-frequency = <1000000>;
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status = "okay";
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}};
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}};
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""".format(spi_csr_base=d["csr_bases"]["spi"])
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# I2C ------------------------------------------------------------------------------------------
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if "i2c0" in d["csr_bases"]:
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dts += """
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i2c0: i2c@{i2c0_csr_base:x} {{
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compatible = "litex,i2c";
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@ -341,10 +344,9 @@ def generate_dts(d):
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}};
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""".format(i2c0_csr_base=d["csr_bases"]["i2c0"])
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# XADC ---------------------------------------------------------------------------------------------
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# XADC -----------------------------------------------------------------------------------------
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if "xadc" in d["csr_bases"]:
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dts += """
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hwmon0: xadc@{xadc_csr_base:x} {{
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compatible = "litex,hwmon-xadc";
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@ -353,11 +355,10 @@ def generate_dts(d):
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}};
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""".format(xadc_csr_base=d["csr_bases"]["xadc"])
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# Framebuffer --------------------------------------------------------------------------------------
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# Framebuffer ----------------------------------------------------------------------------------
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if "framebuffer" in d["csr_bases"]:
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# FIXME: dynamic framebuffer base and size
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# FIXME: Use dynamic framebuffer base and size
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framebuffer_base = 0xc8000000
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framebuffer_width = d["constants"]["litevideo_h_active"]
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framebuffer_height = d["constants"]["litevideo_v_active"]
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@ -370,11 +371,12 @@ def generate_dts(d):
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stride = <{framebuffer_stride}>;
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format = "a8b8g8r8";
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}};
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""".format(framebuffer_base=framebuffer_base,
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framebuffer_width=framebuffer_width,
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framebuffer_height=framebuffer_height,
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framebuffer_size=framebuffer_width * framebuffer_height * 4,
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framebuffer_stride=framebuffer_width * 4)
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""".format(
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framebuffer_base = framebuffer_base,
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framebuffer_width = framebuffer_width,
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framebuffer_height = framebuffer_height,
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framebuffer_size = framebuffer_width * framebuffer_height * 4,
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framebuffer_stride = framebuffer_width * 4)
|
||||
|
||||
dts += """
|
||||
litevideo0: gpu@{litevideo_base:x} {{
|
||||
|
|
@ -392,23 +394,23 @@ def generate_dts(d):
|
|||
litevideo,dma-offset = <0x{litevideo_dma_offset:x}>;
|
||||
litevideo,dma-length = <0x{litevideo_dma_length:x}>;
|
||||
}};
|
||||
""".format(litevideo_base=d["csr_bases"]["framebuffer"],
|
||||
litevideo_pixel_clock=int(d["constants"]["litevideo_pix_clk"] / 1e3),
|
||||
litevideo_h_active=d["constants"]["litevideo_h_active"],
|
||||
litevideo_h_blanking=d["constants"]["litevideo_h_blanking"],
|
||||
litevideo_h_sync=d["constants"]["litevideo_h_sync"],
|
||||
litevideo_h_front_porch=d["constants"]["litevideo_h_front_porch"],
|
||||
litevideo_v_active=d["constants"]["litevideo_v_active"],
|
||||
litevideo_v_blanking=d["constants"]["litevideo_v_blanking"],
|
||||
litevideo_v_sync=d["constants"]["litevideo_v_sync"],
|
||||
litevideo_v_front_porch=d["constants"]["litevideo_v_front_porch"],
|
||||
litevideo_dma_offset=framebuffer_base - d["memories"]["main_ram"]["base"],
|
||||
litevideo_dma_length=framebuffer_width * framebuffer_height * 4)
|
||||
""".format(
|
||||
litevideo_base = d["csr_bases"]["framebuffer"],
|
||||
litevideo_pixel_clock = int(d["constants"]["litevideo_pix_clk"] / 1e3),
|
||||
litevideo_h_active = d["constants"]["litevideo_h_active"],
|
||||
litevideo_h_blanking = d["constants"]["litevideo_h_blanking"],
|
||||
litevideo_h_sync = d["constants"]["litevideo_h_sync"],
|
||||
litevideo_h_front_porch = d["constants"]["litevideo_h_front_porch"],
|
||||
litevideo_v_active = d["constants"]["litevideo_v_active"],
|
||||
litevideo_v_blanking = d["constants"]["litevideo_v_blanking"],
|
||||
litevideo_v_sync = d["constants"]["litevideo_v_sync"],
|
||||
litevideo_v_front_porch = d["constants"]["litevideo_v_front_porch"],
|
||||
litevideo_dma_offset = framebuffer_base - d["memories"]["main_ram"]["base"],
|
||||
litevideo_dma_length = framebuffer_width * framebuffer_height * 4)
|
||||
|
||||
# ICAPBitstream ------------------------------------------------------------------------------------
|
||||
# ICAP Bitstream -------------------------------------------------------------------------------
|
||||
|
||||
if "icap_bit" in d["csr_bases"]:
|
||||
|
||||
dts += """
|
||||
fpga0: icap@{icap_csr_base:x} {{
|
||||
compatible = "litex,fpga-icap";
|
||||
|
|
@ -417,7 +419,7 @@ def generate_dts(d):
|
|||
}};
|
||||
""".format(icap_csr_base=d["csr_bases"]["icap_bit"])
|
||||
|
||||
# CLK ----------------------------------------------------------------------------------------------
|
||||
# Clocking ------------------------------------------------------------------------------------
|
||||
|
||||
def add_clkout(clkout_nr, clk_f, clk_p, clk_dn, clk_dd, clk_margin, clk_margin_exp):
|
||||
return """
|
||||
|
|
@ -433,17 +435,17 @@ def generate_dts(d):
|
|||
litex,clock-margin = <{clk_margin}>;
|
||||
litex,clock-margin-exp = <{clk_margin_exp}>;
|
||||
}};
|
||||
""".format(clkout_nr=clkout_nr,
|
||||
clk_f=clk_f,
|
||||
clk_p=clk_p,
|
||||
clk_dn=clk_dn,
|
||||
clk_dd=clk_dd,
|
||||
clk_margin=clk_margin,
|
||||
clk_margin_exp=clk_margin_exp)
|
||||
""".format(
|
||||
clkout_nr = clkout_nr,
|
||||
clk_f = clk_f,
|
||||
clk_p = clk_p,
|
||||
clk_dn = clk_dn,
|
||||
clk_dd = clk_dd,
|
||||
clk_margin = clk_margin,
|
||||
clk_margin_exp = clk_margin_exp)
|
||||
|
||||
if "mmcm" in d["csr_bases"]:
|
||||
nclkout = d["constants"]["nclkout"]
|
||||
|
||||
dts += """
|
||||
clk0: clk@{mmcm_csr_base:x} {{
|
||||
compatible = "litex,clk";
|
||||
|
|
@ -453,17 +455,13 @@ def generate_dts(d):
|
|||
#size-cells = <0>;
|
||||
clock-output-names =
|
||||
""".format(mmcm_csr_base=d["csr_bases"]["mmcm"])
|
||||
|
||||
for clkout_nr in range(nclkout - 1):
|
||||
|
||||
dts += """
|
||||
"CLKOUT{clkout_nr}",
|
||||
""".format(clkout_nr=clkout_nr)
|
||||
|
||||
dts += """
|
||||
"CLKOUT{nclkout}";
|
||||
""".format(nclkout=(nclkout - 1))
|
||||
|
||||
dts += """
|
||||
litex,lock-timeout = <{mmcm_lock_timeout}>;
|
||||
litex,drdy-timeout = <{mmcm_drdy_timeout}>;
|
||||
|
|
@ -477,15 +475,15 @@ def generate_dts(d):
|
|||
litex,clkout-divide-min = <{clkout_divide_range[0]}>;
|
||||
litex,clkout-divide-max = <{clkout_divide_range[1]}>;
|
||||
litex,vco-margin = <{vco_margin}>;
|
||||
""".format(mmcm_lock_timeout=d["constants"]["mmcm_lock_timeout"],
|
||||
mmcm_drdy_timeout=d["constants"]["mmcm_drdy_timeout"],
|
||||
sys_clk=d["constants"]["config_clock_frequency"],
|
||||
divclk_divide_range=(d["constants"]["divclk_divide_range_min"], d["constants"]["divclk_divide_range_max"]),
|
||||
clkfbout_mult_frange=(d["constants"]["clkfbout_mult_frange_min"], d["constants"]["clkfbout_mult_frange_max"]),
|
||||
vco_freq_range=(d["constants"]["vco_freq_range_min"], d["constants"]["vco_freq_range_max"]),
|
||||
clkout_divide_range=(d["constants"]["clkout_divide_range_min"], d["constants"]["clkout_divide_range_max"]),
|
||||
vco_margin=d["constants"]["vco_margin"])
|
||||
|
||||
""".format(
|
||||
mmcm_lock_timeout = d["constants"]["mmcm_lock_timeout"],
|
||||
mmcm_drdy_timeout = d["constants"]["mmcm_drdy_timeout"],
|
||||
sys_clk = d["constants"]["config_clock_frequency"],
|
||||
divclk_divide_range = (d["constants"]["divclk_divide_range_min"], d["constants"]["divclk_divide_range_max"]),
|
||||
clkfbout_mult_frange = (d["constants"]["clkfbout_mult_frange_min"], d["constants"]["clkfbout_mult_frange_max"]),
|
||||
vco_freq_range = (d["constants"]["vco_freq_range_min"], d["constants"]["vco_freq_range_max"]),
|
||||
clkout_divide_range = (d["constants"]["clkout_divide_range_min"], d["constants"]["clkout_divide_range_max"]),
|
||||
vco_margin = d["constants"]["vco_margin"])
|
||||
for clkout_nr in range(nclkout):
|
||||
dts += add_clkout(clkout_nr,
|
||||
d["constants"]["clkout_def_freq"],
|
||||
|
|
@ -494,35 +492,14 @@ def generate_dts(d):
|
|||
d["constants"]["clkout_def_duty_den"],
|
||||
d["constants"]["clkout_margin"],
|
||||
d["constants"]["clkout_margin_exp"])
|
||||
|
||||
dts += """
|
||||
};"""
|
||||
|
||||
# SDCARD -------------------------------------------------------------------------------------------
|
||||
|
||||
if "sdcore" in d["csr_bases"]:
|
||||
dts += """
|
||||
mmc0: mmc@{mmc_csr_base:x} {{
|
||||
compatible = "litex,mmc";
|
||||
reg = <
|
||||
0x{sdphy_csr_base:x} 0x100
|
||||
0x{sdcore_csr_base:x} 0x100
|
||||
0x{sdblock2mem:x} 0x100
|
||||
0x{sdmem2block:x} 0x100>;
|
||||
bus-width = <0x04>;
|
||||
status = "okay";
|
||||
}};
|
||||
""".format(mmc_csr_base=d["csr_bases"]["sdcore"],
|
||||
sdphy_csr_base=d["csr_bases"]["sdphy"],
|
||||
sdcore_csr_base=d["csr_bases"]["sdcore"],
|
||||
sdblock2mem=d["csr_bases"]["sdblock2mem"],
|
||||
sdmem2block=d["csr_bases"]["sdmem2block"]
|
||||
)
|
||||
dts += """
|
||||
};
|
||||
"""
|
||||
|
||||
# Aliases ------------------------------------------------------------------------------------------
|
||||
# Aliases --------------------------------------------------------------------------------------
|
||||
|
||||
if aliases:
|
||||
dts += """
|
||||
|
|
@ -542,7 +519,7 @@ def generate_dts(d):
|
|||
};
|
||||
"""
|
||||
|
||||
# Leds & switches ----------------------------------------------------------------------------------
|
||||
# Leds & switches ------------------------------------------------------------------------------
|
||||
|
||||
if "leds" in d["csr_bases"]:
|
||||
dts += """
|
||||
|
|
@ -562,7 +539,6 @@ def generate_dts(d):
|
|||
|
||||
return dts
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(description="LiteX's CSR JSON to Linux DTS generator")
|
||||
parser.add_argument("csr_json", help="CSR JSON file")
|
||||
|
|
|
|||
Loading…
Reference in New Issue