update vexii
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8c0f5447ed
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5eeb999694
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@ -132,7 +132,7 @@ class VexiiRiscv(CPU):
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vdir = get_data_mod("cpu", "vexiiriscv").data_location
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vdir = get_data_mod("cpu", "vexiiriscv").data_location
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ndir = os.path.join(vdir, "ext", "VexiiRiscv")
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ndir = os.path.join(vdir, "ext", "VexiiRiscv")
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NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "fpu_internal", "8a239d10", args.update_repo)
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NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "4d2ff4b2", args.update_repo)
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VexiiRiscv.jtag_tap = args.with_jtag_tap
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VexiiRiscv.jtag_tap = args.with_jtag_tap
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VexiiRiscv.jtag_instruction = args.with_jtag_instruction
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VexiiRiscv.jtag_instruction = args.with_jtag_instruction
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