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Merge pull request #1821 from trabucayre/uartbone_add_width 

UARTBone addr width
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enjoy-digital 2023-10-30 15:03:37 +01:00 committed by GitHub
parent b5a9106f56 321254cc38
commit 5efdbd9c20
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2 changed files with 9 additions and 5 deletions
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8
litex/soc/cores/uart.py
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@ -311,7 +311,7 @@ class Stream2Wishbone(LiteXModule):
# # #
assert data_width in [8, 16, 32]
assert address_width in [8, 16, 32]
assert address_width in [8, 16, 32, 64]
cmd = Signal(8, reset_less=True)
incr = Signal()
@ -431,17 +431,17 @@ class Stream2Wishbone(LiteXModule):
class UARTBone(Stream2Wishbone):
def __init__(self, phy, clk_freq, cd="sys"):
def __init__(self, phy, clk_freq, cd="sys", address_width=32):
if cd == "sys":
self.phy = phy
Stream2Wishbone.__init__(self, self.phy, clk_freq=clk_freq)
Stream2Wishbone.__init__(self, self.phy, clk_freq=clk_freq, address_width=address_width)
else:
self.phy = ClockDomainsRenamer(cd)(phy)
self.tx_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from="sys", cd_to=cd)
self.rx_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from=cd, cd_to="sys")
self.comb += self.phy.source.connect(self.rx_cdc.sink)
self.comb += self.tx_cdc.source.connect(self.phy.sink)
Stream2Wishbone.__init__(self, clk_freq=clk_freq)
Stream2Wishbone.__init__(self, clk_freq=clk_freq, address_width=address_width)
self.comb += self.rx_cdc.source.connect(self.sink)
self.comb += self.source.connect(self.tx_cdc.sink)

6
litex/soc/integration/soc.py
View File

@ -1481,7 +1481,11 @@ class LiteXSoC(SoC):
clk_freq = self.sys_clk_freq
self.check_if_exists(name)
uartbone_phy = uart.UARTPHY(self.platform.request(uart_name), clk_freq, baudrate)
uartbone = uart.UARTBone(phy=uartbone_phy, clk_freq=clk_freq, cd=cd)
uartbone = uart.UARTBone(
phy = uartbone_phy,
clk_freq = clk_freq,
cd = cd,
addr_width = self.bus.address_width)
self.add_module(name=f"{name}_phy", module=uartbone_phy)
self.add_module(name=name, module=uartbone)
self.bus.add_master(name=name, master=uartbone.wishbone)