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corelogic/fsm: delayed enters
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1 changed files with 16 additions and 2 deletions
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@ -1,14 +1,28 @@
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from migen.fhdl.structure import *
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from migen.fhdl.structure import *
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class FSM:
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class FSM:
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def __init__(self, *states):
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def __init__(self, *states, delayed_enters=[]):
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self._state_bv = BV(bits_for(len(states)-1))
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nstates = len(states) + sum([d[2] for d in delayed_enters])
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self._state_bv = BV(bits_for(nstates-1))
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self._state = Signal(self._state_bv)
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self._state = Signal(self._state_bv)
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self._next_state = Signal(self._state_bv)
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self._next_state = Signal(self._state_bv)
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for n, state in enumerate(states):
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for n, state in enumerate(states):
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setattr(self, state, Constant(n, self._state_bv))
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setattr(self, state, Constant(n, self._state_bv))
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self.actions = [[] for i in range(len(states))]
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self.actions = [[] for i in range(len(states))]
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for name, target, delay in delayed_enters:
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target_state = getattr(self, target)
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if delay:
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name_state = len(self.actions)
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setattr(self, name, Constant(name_state, self._state_bv))
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for i in range(delay-1):
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self.actions.append([self.next_state(Constant(name_state+i+1), self._state_bv)])
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self.actions.append([self.next_state(target_state)])
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else:
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# alias
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setattr(self, name, getattr(self, target_state))
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def reset_state(self, state):
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def reset_state(self, state):
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self._state.reset = state
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self._state.reset = state
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