software/videomixer: report char position + detected resolution, detect phase at beginning
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1333367de8
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6010308317
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@ -14,20 +14,31 @@
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#define CSR_DVISAMPLER0_D0_PHASE DVISAMPLER0_CSR(0x10)
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#define CSR_DVISAMPLER0_D0_PHASE_RESET DVISAMPLER0_CSR(0x14)
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#define CSR_DVISAMPLER0_D0_CHAR_SYNCED DVISAMPLER0_CSR(0x18)
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#define CSR_DVISAMPLER0_D0_CTL_POS DVISAMPLER0_CSR(0x1C)
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#define CSR_DVISAMPLER0_D1_DELAY_CTL DVISAMPLER0_CSR(0x1C)
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#define CSR_DVISAMPLER0_D1_DELAY_BUSY DVISAMPLER0_CSR(0x20)
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#define CSR_DVISAMPLER0_D1_PHASE DVISAMPLER0_CSR(0x24)
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#define CSR_DVISAMPLER0_D1_PHASE_RESET DVISAMPLER0_CSR(0x28)
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#define CSR_DVISAMPLER0_D1_CHAR_SYNCED DVISAMPLER0_CSR(0x2C)
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#define CSR_DVISAMPLER0_D1_DELAY_CTL DVISAMPLER0_CSR(0x20)
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#define CSR_DVISAMPLER0_D1_DELAY_BUSY DVISAMPLER0_CSR(0x24)
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#define CSR_DVISAMPLER0_D1_PHASE DVISAMPLER0_CSR(0x28)
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#define CSR_DVISAMPLER0_D1_PHASE_RESET DVISAMPLER0_CSR(0x2C)
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#define CSR_DVISAMPLER0_D1_CHAR_SYNCED DVISAMPLER0_CSR(0x30)
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#define CSR_DVISAMPLER0_D1_CTL_POS DVISAMPLER0_CSR(0x34)
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#define CSR_DVISAMPLER0_D2_DELAY_CTL DVISAMPLER0_CSR(0x30)
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#define CSR_DVISAMPLER0_D2_DELAY_BUSY DVISAMPLER0_CSR(0x34)
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#define CSR_DVISAMPLER0_D2_PHASE DVISAMPLER0_CSR(0x38)
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#define CSR_DVISAMPLER0_D2_PHASE_RESET DVISAMPLER0_CSR(0x3C)
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#define CSR_DVISAMPLER0_D2_CHAR_SYNCED DVISAMPLER0_CSR(0x40)
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#define CSR_DVISAMPLER0_D2_DELAY_CTL DVISAMPLER0_CSR(0x38)
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#define CSR_DVISAMPLER0_D2_DELAY_BUSY DVISAMPLER0_CSR(0x3C)
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#define CSR_DVISAMPLER0_D2_PHASE DVISAMPLER0_CSR(0x40)
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#define CSR_DVISAMPLER0_D2_PHASE_RESET DVISAMPLER0_CSR(0x44)
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#define CSR_DVISAMPLER0_D2_CHAR_SYNCED DVISAMPLER0_CSR(0x48)
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#define CSR_DVISAMPLER0_D2_CTL_POS DVISAMPLER0_CSR(0x4C)
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#define CSR_DVISAMPLER0_CHAN_SYNCED DVISAMPLER0_CSR(0x44)
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#define CSR_DVISAMPLER0_CHAN_SYNCED DVISAMPLER0_CSR(0x50)
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#define CSR_DVISAMPLER0_HRESH DVISAMPLER0_CSR(0x54)
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#define CSR_DVISAMPLER0_HRESL DVISAMPLER0_CSR(0x58)
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#define CSR_DVISAMPLER0_VRESH DVISAMPLER0_CSR(0x5C)
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#define CSR_DVISAMPLER0_VRESL DVISAMPLER0_CSR(0x60)
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#define CSR_DVISAMPLER0_DECNT2 DVISAMPLER0_CSR(0x64)
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#define CSR_DVISAMPLER0_DECNT1 DVISAMPLER0_CSR(0x68)
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#define CSR_DVISAMPLER0_DECNT0 DVISAMPLER0_CSR(0x6C)
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#define DVISAMPLER_DELAY_CAL 0x01
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#define DVISAMPLER_DELAY_RST 0x02
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@ -1,4 +1,5 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include <irq.h>
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#include <uart.h>
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@ -6,6 +7,21 @@
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static int d0, d1, d2;
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static void print_status(void)
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{
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printf("Ph: %4d %4d %4d // %d%d%d [%d %d %d] // %d // %dx%d // %d\n", d0, d1, d2,
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CSR_DVISAMPLER0_D0_CHAR_SYNCED,
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CSR_DVISAMPLER0_D1_CHAR_SYNCED,
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CSR_DVISAMPLER0_D2_CHAR_SYNCED,
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CSR_DVISAMPLER0_D0_CTL_POS,
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CSR_DVISAMPLER0_D1_CTL_POS,
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CSR_DVISAMPLER0_D2_CTL_POS,
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CSR_DVISAMPLER0_CHAN_SYNCED,
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(CSR_DVISAMPLER0_HRESH << 8) | CSR_DVISAMPLER0_HRESL,
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(CSR_DVISAMPLER0_VRESH << 8) | CSR_DVISAMPLER0_VRESL,
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(CSR_DVISAMPLER0_DECNT2 << 16) | (CSR_DVISAMPLER0_DECNT1 << 8) | CSR_DVISAMPLER0_DECNT0);
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}
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static void calibrate_delays(void)
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{
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CSR_DVISAMPLER0_D0_DELAY_CTL = DVISAMPLER_DELAY_CAL;
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@ -60,28 +76,46 @@ static void adjust_phase(void)
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CSR_DVISAMPLER0_D2_PHASE_RESET = 1;
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break;
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}
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printf("Ph: %4d %4d %4d // %d%d%d // %d\n", d0, d1, d2,
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CSR_DVISAMPLER0_D0_CHAR_SYNCED,
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CSR_DVISAMPLER0_D1_CHAR_SYNCED,
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CSR_DVISAMPLER0_D2_CHAR_SYNCED,
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CSR_DVISAMPLER0_CHAN_SYNCED);
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}
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static int init_phase(void)
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{
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int od0, od1, od2;
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int i, j;
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for(i=0;i<100;i++) {
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od0 = d0;
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od1 = d1;
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od2 = d2;
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for(j=0;j<1000;j++)
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adjust_phase();
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if((abs(d0 - od0) < 4) && (abs(d1 - od1) < 4) && (abs(d2 - od2) < 4))
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return 1;
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}
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return 0;
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}
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static void vmix(void)
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{
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int i;
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unsigned int counter;
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while(1) {
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while(!CSR_DVISAMPLER0_PLL_LOCKED);
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printf("PLL locked\n");
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calibrate_delays();
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adjust_phase();
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if(init_phase())
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printf("Phase init OK\n");
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else
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printf("Phase did not settle\n");
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print_status();
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counter = 0;
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while(CSR_DVISAMPLER0_PLL_LOCKED) {
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counter++;
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if(counter == 200000) {
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adjust_phase();
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if(counter == 2000000) {
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print_status();
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//adjust_phase();
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counter = 0;
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}
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}
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