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adapt LiteSATA to new SoC

This commit is contained in:
Florent Kermarrec 2015-04-01 22:52:19 +02:00
parent dcdf5df4de
commit 60124be293
1 changed files with 3 additions and 1 deletions
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4
misoclib/mem/litesata/example_designs/make.py
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@ -69,6 +69,8 @@ if __name__ == "__main__":
top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
soc = top_class(platform, **top_kwargs)
soc.finalize()
memory_regions = soc.get_memory_regions()
csr_regions = soc.get_csr_regions()
# decode actions
action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"]
@ -124,7 +126,7 @@ BIST: {}
subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]:
csr_csv = cpuif.get_csr_csv(soc.get_csr_regions())
csr_csv = cpuif.get_csr_csv(csr_regions)
write_to_file(args.csr_csv, csr_csv)
if actions["build-core"]: