liteeth: adapt to new ModuleTransformer
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@ -23,7 +23,7 @@ class LiteEthMACWishboneInterface(Module, AutoCSR):
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wb_rx_sram_ifs = [wishbone.SRAM(self.sram.writer.mems[n], read_only=True)
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for n in range(nrxslots)]
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# TODO: FullMemoryWE should move to Mibuild
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wb_tx_sram_ifs = [FullMemoryWE(wishbone.SRAM(self.sram.reader.mems[n], read_only=False))
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wb_tx_sram_ifs = [FullMemoryWE()(wishbone.SRAM(self.sram.reader.mems[n], read_only=False))
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for n in range(ntxslots)]
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wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs
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