Use migen.fhdl.std

milkymist/asmicon/__init__.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.bus import dfi, asmibus
 
 from milkymist.asmicon.refresher import *

milkymist/asmicon/bankmachine.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.bus.asmibus import *
 from migen.genlib.roundrobin import *
 from migen.genlib.fsm import FSM

milkymist/asmicon/multiplexer.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.genlib.roundrobin import *
 from migen.genlib.misc import optree
 from migen.genlib.fsm import FSM
@@ -26,7 +25,7 @@ class _CommandChooser(Module):
 		self.want_reads = Signal()
 		self.want_writes = Signal()
 		# NB: cas_n/ras_n/we_n are 1 when stb is inactive
-		self.cmd = CommandRequestRW(len(requests[0].a), len(requests[0].ba), tagbits)
+		self.cmd = CommandRequestRW(flen(requests[0].a), flen(requests[0].ba), tagbits)
 	
 		###
 
@@ -83,7 +82,7 @@ class _Steerer(Module):
 
 class _Datapath(Module):
 	def __init__(self, timing_settings, command, dfi, hub):
-		tagbits = len(hub.tag_call)
+		tagbits = flen(hub.tag_call)
 		
 		rd_valid = Signal()
 		rd_tag = Signal(tagbits)
@@ -136,7 +135,7 @@ class Multiplexer(Module):
 	
 		# Command choosing
 		requests = [bm.cmd for bm in bank_machines]
-		tagbits = len(hub.tag_call)
+		tagbits = flen(hub.tag_call)
 		choose_cmd = _CommandChooser(requests, tagbits)
 		choose_req = _CommandChooser(requests, tagbits)
 		self.comb += [

milkymist/asmicon/refresher.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.genlib.misc import timeline
 from migen.genlib.fsm import FSM
 

milkymist/asmiprobe/__init__.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.bank.description import *
 
 class ASMIprobe(Module):

milkymist/counteradc/__init__.py

@@ -1,5 +1,6 @@
-from migen.fhdl.structure import *
+import collections
-from migen.fhdl.module import Module
+
+from migen.fhdl.std import *
 from migen.bank.description import *
 from migen.genlib.misc import optree
 from migen.genlib.cdc import MultiReg

milkymist/dfii/__init__.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.bus import dfi
 from migen.bank.description import *
 
@@ -7,10 +6,10 @@ class PhaseInjector(Module, AutoCSR):
 	def __init__(self, phase):
 		self._command = CSRStorage(6) # cs, we, cas, ras, wren, rden
 		self._command_issue = CSR()
-		self._address = CSRStorage(len(phase.address))
+		self._address = CSRStorage(flen(phase.address))
-		self._baddress = CSRStorage(len(phase.bank))
+		self._baddress = CSRStorage(flen(phase.bank))
-		self._wrdata = CSRStorage(len(phase.wrdata))
+		self._wrdata = CSRStorage(flen(phase.wrdata))
-		self._rddata = CSRStatus(len(phase.rddata))
+		self._rddata = CSRStatus(flen(phase.rddata))
 	
 		###
 

milkymist/dvisampler/__init__.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.bank.description import AutoCSR
 
 from milkymist.dvisampler.edid import EDID

milkymist/dvisampler/analysis.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.record import Record

milkymist/dvisampler/chansync.py

@@ -1,6 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.specials import Memory
-from migen.fhdl.module import Module
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fifo import _inc
 from migen.genlib.record import Record, layout_len

milkymist/dvisampler/charsync.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.genlib.cdc import MultiReg
 from migen.genlib.misc import optree
 from migen.bank.description import *

milkymist/dvisampler/clocking.py

@@ -1,6 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
-from migen.fhdl.specials import Instance
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 

milkymist/dvisampler/datacapture.py

@@ -1,6 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
-from migen.fhdl.specials import Instance
 from migen.genlib.cdc import MultiReg, PulseSynchronizer
 from migen.bank.description import *
 

milkymist/dvisampler/debug.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.record import layout_len
 from migen.bank.description import AutoCSR

milkymist/dvisampler/decoding.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.genlib.record import Record
 
 from milkymist.dvisampler.common import control_tokens, channel_layout

milkymist/dvisampler/dma.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.genlib.fsm import FSM
 from migen.bank.description import *
 from migen.bank.eventmanager import *

milkymist/dvisampler/edid.py

@@ -1,6 +1,5 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.specials import Memory, Tristate
+from migen.fhdl.specials import Tristate
-from migen.fhdl.module import Module
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fsm import FSM
 from migen.genlib.misc import chooser

milkymist/dvisampler/wer.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.bank.description import *
 from migen.genlib.misc import optree
 from migen.genlib.cdc import PulseSynchronizer

milkymist/framebuffer/__init__.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.flow.actor import *
 from migen.flow.network import *
 from migen.bank.description import CSRStorage, AutoCSR

milkymist/framebuffer/lib.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.genlib.record import Record
 from migen.genlib.fifo import AsyncFIFO
 from migen.flow.actor import *

milkymist/gpio/__init__.py

@@ -1,16 +1,15 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 
 class GPIOIn(Module, AutoCSR):
 	def __init__(self, signal):
-		self._r_in = CSRStatus(len(signal))
+		self._r_in = CSRStatus(flen(signal))
 		self.specials += MultiReg(signal, self._r_in.status)
 
 class GPIOOut(Module, AutoCSR):
 	def __init__(self, signal):
-		self._r_out = CSRStorage(len(signal))
+		self._r_out = CSRStorage(flen(signal))
 		self.comb += signal.eq(self._r_out.storage)
 
 class Blinker(Module):

milkymist/identifier/__init__.py

@@ -1,7 +1,6 @@
 import re
 
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.bank.description import *
 
 def encode_version(version):

milkymist/lm32/__init__.py

@@ -1,6 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.specials import Instance
-from migen.fhdl.module import Module
 from migen.bus import wishbone
 
 class LM32(Module):

milkymist/m1crg/__init__.py

@@ -1,8 +1,6 @@
 from fractions import Fraction
 
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.specials import Instance
-from migen.fhdl.module import Module
 from migen.bank.description import *
 
 class M1CRG(Module, AutoCSR):

milkymist/minimac3/__init__.py

@@ -1,6 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.specials import Instance
-from migen.fhdl.module import Module
 from migen.bank.description import *
 from migen.bank.eventmanager import *
 from migen.bus import wishbone

milkymist/norflash/__init__.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.bus import wishbone
 from migen.genlib.misc import timeline
 
@@ -9,7 +8,7 @@ class NorFlash(Module):
 	
 		###
 
-		adr_width = len(pads.adr) + 1
+		adr_width = flen(pads.adr) + 1
 		self.comb += [pads.oe_n.eq(0), pads.we_n.eq(1),
 			pads.ce_n.eq(0)]
 		self.sync += timeline(self.bus.cyc & self.bus.stb, [

milkymist/s6ddrphy/__init__.py

@@ -1,20 +1,18 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.specials import Instance
-from migen.fhdl.module import Module
 from migen.bus import dfi
 
 class S6DDRPHY(Module):
 	def __init__(self, pads):
-		self.dfi = dfi.Interface(len(pads.a), len(pads.ba), 2*len(pads.dq), 2)
+		self.dfi = dfi.Interface(flen(pads.a), flen(pads.ba), 2*flen(pads.dq), 2)
 		self.clk4x_wr_strb = Signal()
 		self.clk4x_rd_strb = Signal()
 
 		###
 
 		inst_items = [
-			Instance.Parameter("NUM_AD", len(pads.a)),
+			Instance.Parameter("NUM_AD", flen(pads.a)),
-			Instance.Parameter("NUM_BA", len(pads.ba)),
+			Instance.Parameter("NUM_BA", flen(pads.ba)),
-			Instance.Parameter("NUM_D", 2*len(pads.dq)),
+			Instance.Parameter("NUM_D", 2*flen(pads.dq)),
 
 			Instance.Input("sys_clk", ClockSignal()),
 			Instance.Input("clk2x_270", ClockSignal("sys2x_270")),

milkymist/timer/__init__.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.bank.description import *
 from migen.bank.eventmanager import *
 

milkymist/uart/__init__.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 from migen.bank.eventmanager import *

tb/asmicon/asmicon.py

@@ -1,4 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.bus.asmibus import *
 from migen.sim.generic import Simulator, TopLevel
 

tb/asmicon/asmicon_wb.py

@@ -1,4 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.bus import wishbone, wishbone2asmi, asmibus
 from migen.sim.generic import Simulator, TopLevel
 

tb/asmicon/bankmachine.py

@@ -1,4 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.bus.asmibus import *
 from migen.sim.generic import Simulator, TopLevel
 

tb/asmicon/common.py

@@ -1,7 +1,7 @@
 from fractions import Fraction
 from math import ceil
 
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.sim.generic import Proxy
 
 from milkymist import asmicon

tb/asmicon/refresher.py

@@ -1,6 +1,6 @@
 from random import Random
 
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.sim.generic import Simulator, TopLevel
 
 from milkymist.asmicon.refresher import *

tb/asmicon/selector.py

@@ -1,6 +1,6 @@
 from random import Random
 
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.bus.asmibus import *
 from migen.sim.generic import Simulator, TopLevel
 

tb/dvisampler/chansync.py

@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.sim.generic import *
 
 from milkymist.dvisampler.chansync import ChanSync

tb/framebuffer/framebuffer.py

@@ -1,4 +1,4 @@
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.bus import asmibus
 from migen.sim.generic import Simulator
 

top.py

@@ -2,8 +2,7 @@ from fractions import Fraction
 from math import ceil
 from operator import itemgetter
 
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
-from migen.fhdl.module import Module
 from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
 from migen.bank import csrgen