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soc/cores/spi_mmap: adjust CSR mapping to better suit drivers

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Currently the TX_RX_ENGINE CSR register lives below the
slot registers which are dynamic in length (based on how
many slots (chip selects) are configured in the gateware).

Move the TX_RX_ENGINE CSR to above the SLOT configuration
registers so TX_RX_ENGINE never moves.

This makes for an easier and cleaner driver.
This commit is contained in:
Richard Tucker 2023-10-19 12:21:47 +11:00 committed by Andrew Dennison
parent dc78c3f47b
commit 6170c90459
1 changed files with 11 additions and 10 deletions
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21
litex/soc/cores/spi/spi_mmap.py
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@ -239,6 +239,7 @@ class SPICtrl(LiteXModule):
default_slot_bitorder = SPI_SLOT_BITORDER_MSB_FIRST, default_slot_bitorder = SPI_SLOT_BITORDER_MSB_FIRST,
default_slot_loopback = 0b1, default_slot_loopback = 0b1,
default_slot_divider = 2, default_slot_divider = 2,
default_enable = 0b1,
): ):
self.nslots = nslots self.nslots = nslots
self.slot_controls = [] self.slot_controls = []
@ -302,6 +303,13 @@ class SPICtrl(LiteXModule):
self.ev.rx.trigger.eq(self.rx_status.fields.level > self.rx_control.fields.threshold), self.ev.rx.trigger.eq(self.rx_status.fields.level > self.rx_control.fields.threshold),
] ]
self.engine = CSRStorage(fields=[
CSRField("enable", size=1, offset=0, values=[
("``0b0``", "SPI Engine Disabled."),
("``0b1``", "SPI Engine Enabled."),
], reset=default_enable),
])
# Create Slots Control/Status registers. # Create Slots Control/Status registers.
for slot in range(nslots): for slot in range(nslots):
control = CSRStorage(name=f"slot_control{slot}", fields=[ control = CSRStorage(name=f"slot_control{slot}", fields=[
@ -487,7 +495,7 @@ class SPIRXMMAP(LiteXModule):
# SPI Engine --------------------------------------------------------------------------------------- # SPI Engine ---------------------------------------------------------------------------------------
class SPIEngine(LiteXModule): class SPIEngine(LiteXModule):
def __init__(self, pads, ctrl, data_width, sys_clk_freq, default_enable=0b1): def __init__(self, pads, ctrl, data_width, sys_clk_freq):
self.sink = sink = stream.Endpoint(spi_layout( self.sink = sink = stream.Endpoint(spi_layout(
data_width = data_width, data_width = data_width,
be_width = data_width//8, be_width = data_width//8,
@ -499,13 +507,6 @@ class SPIEngine(LiteXModule):
cs_width = len(pads.cs_n) cs_width = len(pads.cs_n)
)) ))
self.control = CSRStorage(fields=[
CSRField("enable", size=1, offset=0, values=[
("``0b0``", "SPI Engine Disabled."),
("``0b1``", "SPI Engine Enabled."),
], reset=default_enable),
])
# # # # # #
# SPI Master. # SPI Master.
@ -544,7 +545,7 @@ class SPIEngine(LiteXModule):
] ]
# SPI CS. (Use Manual CS to allow back-to-back Xfers). # SPI CS. (Use Manual CS to allow back-to-back Xfers).
self.comb += If(self.control.fields.enable & sink.valid, self.comb += If(ctrl.engine.fields.enable & sink.valid,
spi.cs.eq(sink.cs) spi.cs.eq(sink.cs)
) )
@ -555,7 +556,7 @@ class SPIEngine(LiteXModule):
# Control-Path. # Control-Path.
self.fsm = fsm = FSM(reset_state="START") self.fsm = fsm = FSM(reset_state="START")
fsm.act("START", fsm.act("START",
If(self.control.fields.enable & sink.valid, If(ctrl.engine.fields.enable & sink.valid,
spi.start.eq(1), spi.start.eq(1),
NextState("XFER") NextState("XFER")
) )