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fhdl/memory/verilog: Rename ns -> namespace and minor cleanup.

This commit is contained in:
Florent Kermarrec 2022-05-06 19:34:21 +02:00
parent b83e84c78a
commit 61eead5170
2 changed files with 15 additions and 8 deletions
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7
litex/gen/fhdl/memory.py
View File

@ -12,14 +12,15 @@ from migen.fhdl.tools import *
from migen.fhdl.verilog import _printexpr as verilog_printexpr
from migen.fhdl.specials import *
def memory_emit_verilog(memory, ns, add_data_file):
def memory_emit_verilog(memory, namespace, add_data_file):
# Helpers.
# --------
def gn(e):
if isinstance(e, Memory):
return ns.get_name(e)
return namespace.get_name(e)
else:
return verilog_printexpr(ns, e)[0]
return verilog_printexpr(namespace, e)[0]
# Parameters.
# -----------

16
litex/gen/fhdl/verilog.py
View File

@ -490,7 +490,7 @@ def _print_synchronous_logic(f, ns):
# SPECIALS #
# ------------------------------------------------------------------------------------------------ #
def _print_specials(overrides, specials, ns, add_data_file, attr_translate):
def _print_specials(name, overrides, specials, namespace, add_data_file, attr_translate):
r = ""
for special in sorted(specials, key=lambda x: x.duid):
if hasattr(special, "attr"):
@ -500,9 +500,9 @@ def _print_specials(overrides, specials, ns, add_data_file, attr_translate):
# Replace Migen Memory's emit_verilog with LiteX's implementation.
if isinstance(special, Memory):
from litex.gen.fhdl.memory import memory_emit_verilog
pr = memory_emit_verilog(special, ns, add_data_file)
pr = memory_emit_verilog(special, namespace, add_data_file)
else:
pr = call_special_classmethod(overrides, special, "emit_verilog", ns, add_data_file)
pr = call_special_classmethod(overrides, special, "emit_verilog", namespace, add_data_file)
if pr is None:
raise NotImplementedError("Special " + str(special) + " failed to implement emit_verilog")
r += pr
@ -610,8 +610,14 @@ def convert(f, ios=set(), name="top", platform=None,
# Specials
verilog += _print_separator("Specialized Logic")
verilog += _print_specials(special_overrides, f.specials - lowered_specials,
ns, r.add_data_file, attr_translate)
verilog += _print_specials(
name = name,
overrides =special_overrides,
specials = f.specials - lowered_specials,
namespace = ns,
add_data_file = r.add_data_file,
attr_translate = attr_translate
)
# Module End.
verilog += "endmodule\n"