fhdl/memory/verilog: Rename ns -> namespace and minor cleanup.
This commit is contained in:
parent
b83e84c78a
commit
61eead5170
|
@ -12,14 +12,15 @@ from migen.fhdl.tools import *
|
||||||
from migen.fhdl.verilog import _printexpr as verilog_printexpr
|
from migen.fhdl.verilog import _printexpr as verilog_printexpr
|
||||||
from migen.fhdl.specials import *
|
from migen.fhdl.specials import *
|
||||||
|
|
||||||
def memory_emit_verilog(memory, ns, add_data_file):
|
|
||||||
|
def memory_emit_verilog(memory, namespace, add_data_file):
|
||||||
# Helpers.
|
# Helpers.
|
||||||
# --------
|
# --------
|
||||||
def gn(e):
|
def gn(e):
|
||||||
if isinstance(e, Memory):
|
if isinstance(e, Memory):
|
||||||
return ns.get_name(e)
|
return namespace.get_name(e)
|
||||||
else:
|
else:
|
||||||
return verilog_printexpr(ns, e)[0]
|
return verilog_printexpr(namespace, e)[0]
|
||||||
|
|
||||||
# Parameters.
|
# Parameters.
|
||||||
# -----------
|
# -----------
|
||||||
|
|
|
@ -490,7 +490,7 @@ def _print_synchronous_logic(f, ns):
|
||||||
# SPECIALS #
|
# SPECIALS #
|
||||||
# ------------------------------------------------------------------------------------------------ #
|
# ------------------------------------------------------------------------------------------------ #
|
||||||
|
|
||||||
def _print_specials(overrides, specials, ns, add_data_file, attr_translate):
|
def _print_specials(name, overrides, specials, namespace, add_data_file, attr_translate):
|
||||||
r = ""
|
r = ""
|
||||||
for special in sorted(specials, key=lambda x: x.duid):
|
for special in sorted(specials, key=lambda x: x.duid):
|
||||||
if hasattr(special, "attr"):
|
if hasattr(special, "attr"):
|
||||||
|
@ -500,9 +500,9 @@ def _print_specials(overrides, specials, ns, add_data_file, attr_translate):
|
||||||
# Replace Migen Memory's emit_verilog with LiteX's implementation.
|
# Replace Migen Memory's emit_verilog with LiteX's implementation.
|
||||||
if isinstance(special, Memory):
|
if isinstance(special, Memory):
|
||||||
from litex.gen.fhdl.memory import memory_emit_verilog
|
from litex.gen.fhdl.memory import memory_emit_verilog
|
||||||
pr = memory_emit_verilog(special, ns, add_data_file)
|
pr = memory_emit_verilog(special, namespace, add_data_file)
|
||||||
else:
|
else:
|
||||||
pr = call_special_classmethod(overrides, special, "emit_verilog", ns, add_data_file)
|
pr = call_special_classmethod(overrides, special, "emit_verilog", namespace, add_data_file)
|
||||||
if pr is None:
|
if pr is None:
|
||||||
raise NotImplementedError("Special " + str(special) + " failed to implement emit_verilog")
|
raise NotImplementedError("Special " + str(special) + " failed to implement emit_verilog")
|
||||||
r += pr
|
r += pr
|
||||||
|
@ -610,8 +610,14 @@ def convert(f, ios=set(), name="top", platform=None,
|
||||||
|
|
||||||
# Specials
|
# Specials
|
||||||
verilog += _print_separator("Specialized Logic")
|
verilog += _print_separator("Specialized Logic")
|
||||||
verilog += _print_specials(special_overrides, f.specials - lowered_specials,
|
verilog += _print_specials(
|
||||||
ns, r.add_data_file, attr_translate)
|
name = name,
|
||||||
|
overrides =special_overrides,
|
||||||
|
specials = f.specials - lowered_specials,
|
||||||
|
namespace = ns,
|
||||||
|
add_data_file = r.add_data_file,
|
||||||
|
attr_translate = attr_translate
|
||||||
|
)
|
||||||
|
|
||||||
# Module End.
|
# Module End.
|
||||||
verilog += "endmodule\n"
|
verilog += "endmodule\n"
|
||||||
|
|
Loading…
Reference in New Issue