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fhdl/verilog: do not attempt to initialize instance and mem output signals

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This commit is contained in:
Sebastien Bourdeauducq 2012-04-02 12:59:42 +02:00
parent 6e3b25ebb6
commit 623e8e436a
1 changed files with 6 additions and 2 deletions
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8
migen/fhdl/verilog.py
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@ -220,9 +220,13 @@ def _printmemories(f, ns, handler, clk):
r += handler(memory, ns, clk)
return r
def _printinit(f, exclude, ns):
def _printinit(f, ios, ns):
r = ""
signals = list_signals(f) - exclude - list_targets(f)
signals = list_signals(f) \
- ios \
- list_targets(f) \
- list_inst_ios(f, False, True, False) \
- list_mem_ios(f, False, True)
if signals:
r += "initial begin\n"
for s in signals: