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liteeth: move mac to core

This commit is contained in:
Florent Kermarrec 2015-05-02 12:55:51 +02:00
parent a4617014f4
commit 63b8797978
18 changed files with 12 additions and 12 deletions
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2
misoclib/com/liteeth/core/__init__.py
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@ -1,5 +1,5 @@
from misoclib.com.liteeth.common import * from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.mac import LiteEthMAC from misoclib.com.liteeth.core.mac import LiteEthMAC
from misoclib.com.liteeth.core.arp import LiteEthARP from misoclib.com.liteeth.core.arp import LiteEthARP
from misoclib.com.liteeth.core.ip import LiteEthIP from misoclib.com.liteeth.core.ip import LiteEthIP
from misoclib.com.liteeth.core.udp import LiteEthUDP from misoclib.com.liteeth.core.udp import LiteEthUDP

6
misoclib/com/liteeth/mac/__init__.py → misoclib/com/liteeth/core/mac/__init__.py
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@ -1,7 +1,7 @@
from misoclib.com.liteeth.common import * from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.mac.common import * from misoclib.com.liteeth.core.mac.common import *
from misoclib.com.liteeth.mac.core import LiteEthMACCore from misoclib.com.liteeth.core.mac.core import LiteEthMACCore
from misoclib.com.liteeth.mac.frontend.wishbone import LiteEthMACWishboneInterface from misoclib.com.liteeth.core.mac.frontend.wishbone import LiteEthMACWishboneInterface
class LiteEthMAC(Module, AutoCSR): class LiteEthMAC(Module, AutoCSR):

0
misoclib/com/liteeth/mac/common.py → misoclib/com/liteeth/core/mac/common.py
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2
misoclib/com/liteeth/mac/core/__init__.py → misoclib/com/liteeth/core/mac/core/__init__.py
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@ -1,5 +1,5 @@
from misoclib.com.liteeth.common import * from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.mac.core import gap, preamble, crc, padding, last_be from misoclib.com.liteeth.core.mac.core import gap, preamble, crc, padding, last_be
from misoclib.com.liteeth.phy.sim import LiteEthPHYSim from misoclib.com.liteeth.phy.sim import LiteEthPHYSim

0
misoclib/com/liteeth/mac/core/crc.py → misoclib/com/liteeth/core/mac/core/crc.py
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0
misoclib/com/liteeth/mac/core/gap.py → misoclib/com/liteeth/core/mac/core/gap.py
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0
misoclib/com/liteeth/mac/core/last_be.py → misoclib/com/liteeth/core/mac/core/last_be.py
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0
misoclib/com/liteeth/mac/core/padding.py → misoclib/com/liteeth/core/mac/core/padding.py
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0
misoclib/com/liteeth/mac/core/preamble.py → misoclib/com/liteeth/core/mac/core/preamble.py
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0
misoclib/com/liteeth/mac/frontend/__init__.py → misoclib/com/liteeth/core/mac/frontend/__init__.py
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0
misoclib/com/liteeth/mac/frontend/sram.py → misoclib/com/liteeth/core/mac/frontend/sram.py
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2
misoclib/com/liteeth/mac/frontend/wishbone.py → misoclib/com/liteeth/core/mac/frontend/wishbone.py
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@ -1,5 +1,5 @@
from misoclib.com.liteeth.common import * from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.mac.frontend import sram from misoclib.com.liteeth.core.mac.frontend import sram
from migen.bus import wishbone from migen.bus import wishbone
from migen.fhdl.simplify import FullMemoryWE from migen.fhdl.simplify import FullMemoryWE

2
misoclib/com/liteeth/test/arp_tb.py
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@ -4,7 +4,7 @@ from migen.bus.transactions import *
from migen.sim.generic import run_simulation from migen.sim.generic import run_simulation
from misoclib.com.liteeth.common import * from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.mac import LiteEthMAC from misoclib.com.liteeth.core.mac import LiteEthMAC
from misoclib.com.liteeth.core.arp import LiteEthARP from misoclib.com.liteeth.core.arp import LiteEthARP
from misoclib.com.liteeth.test.common import * from misoclib.com.liteeth.test.common import *

2
misoclib/com/liteeth/test/mac_core_tb.py
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@ -4,7 +4,7 @@ from migen.bus.transactions import *
from migen.sim.generic import run_simulation from migen.sim.generic import run_simulation
from misoclib.com.liteeth.common import * from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.mac.core import LiteEthMACCore from misoclib.com.liteeth.core.mac.core import LiteEthMACCore
from misoclib.com.liteeth.test.common import * from misoclib.com.liteeth.test.common import *
from misoclib.com.liteeth.test.model import phy, mac from misoclib.com.liteeth.test.model import phy, mac

2
misoclib/com/liteeth/test/mac_wishbone_tb.py
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@ -4,7 +4,7 @@ from migen.bus.transactions import *
from migen.sim.generic import run_simulation from migen.sim.generic import run_simulation
from misoclib.com.liteeth.common import * from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.mac import LiteEthMAC from misoclib.com.liteeth.core.mac import LiteEthMAC
from misoclib.com.liteeth.test.common import * from misoclib.com.liteeth.test.common import *
from misoclib.com.liteeth.test.model import phy, mac from misoclib.com.liteeth.test.model import phy, mac

2
targets/kc705.py
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@ -9,7 +9,7 @@ from misoclib.soc import mem_decoder
from misoclib.soc.sdram import SDRAMSoC from misoclib.soc.sdram import SDRAMSoC
from misoclib.com.liteeth.phy import LiteEthPHY from misoclib.com.liteeth.phy import LiteEthPHY
from misoclib.com.liteeth.mac import LiteEthMAC from misoclib.com.liteeth.core.mac import LiteEthMAC
class _CRG(Module): class _CRG(Module):

2
targets/mlabs_video.py
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@ -15,7 +15,7 @@ from misoclib.soc import mem_decoder
from misoclib.soc.sdram import SDRAMSoC from misoclib.soc.sdram import SDRAMSoC
from misoclib.com import gpio from misoclib.com import gpio
from misoclib.com.liteeth.phy import LiteEthPHY from misoclib.com.liteeth.phy import LiteEthPHY
from misoclib.com.liteeth.mac import LiteEthMAC from misoclib.com.liteeth.core.mac import LiteEthMAC
class _MXClockPads: class _MXClockPads:

2
targets/simple.py
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@ -4,7 +4,7 @@ from migen.genlib.io import CRG
from misoclib.soc import SoC, mem_decoder from misoclib.soc import SoC, mem_decoder
from misoclib.com.liteeth.phy import LiteEthPHY from misoclib.com.liteeth.phy import LiteEthPHY
from misoclib.com.liteeth.mac import LiteEthMAC from misoclib.com.liteeth.core.mac import LiteEthMAC
class BaseSoC(SoC): class BaseSoC(SoC):