liteeth: move mac to core

misoclib/com/liteeth/core/__init__.py

@@ -1,5 +1,5 @@
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac import LiteEthMAC
+from misoclib.com.liteeth.core.mac import LiteEthMAC
 from misoclib.com.liteeth.core.arp import LiteEthARP
 from misoclib.com.liteeth.core.ip import LiteEthIP
 from misoclib.com.liteeth.core.udp import LiteEthUDP

misoclib/com/liteeth/core/mac/__init__.py

@@ -1,7 +1,7 @@
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac.common import *
-from misoclib.com.liteeth.mac.core import LiteEthMACCore
-from misoclib.com.liteeth.mac.frontend.wishbone import LiteEthMACWishboneInterface
+from misoclib.com.liteeth.core.mac.common import *
+from misoclib.com.liteeth.core.mac.core import LiteEthMACCore
+from misoclib.com.liteeth.core.mac.frontend.wishbone import LiteEthMACWishboneInterface
 
 
 class LiteEthMAC(Module, AutoCSR):

misoclib/com/liteeth/core/mac/core/__init__.py

@@ -1,5 +1,5 @@
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac.core import gap, preamble, crc, padding, last_be
+from misoclib.com.liteeth.core.mac.core import gap, preamble, crc, padding, last_be
 from misoclib.com.liteeth.phy.sim import LiteEthPHYSim
 
 

misoclib/com/liteeth/core/mac/frontend/wishbone.py

@@ -1,5 +1,5 @@
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac.frontend import sram
+from misoclib.com.liteeth.core.mac.frontend import sram
 
 from migen.bus import wishbone
 from migen.fhdl.simplify import FullMemoryWE

misoclib/com/liteeth/test/arp_tb.py

@@ -4,7 +4,7 @@ from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac import LiteEthMAC
+from misoclib.com.liteeth.core.mac import LiteEthMAC
 from misoclib.com.liteeth.core.arp import LiteEthARP
 
 from misoclib.com.liteeth.test.common import *

misoclib/com/liteeth/test/mac_core_tb.py

@@ -4,7 +4,7 @@ from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac.core import LiteEthMACCore
+from misoclib.com.liteeth.core.mac.core import LiteEthMACCore
 
 from misoclib.com.liteeth.test.common import *
 from misoclib.com.liteeth.test.model import phy, mac

misoclib/com/liteeth/test/mac_wishbone_tb.py

@@ -4,7 +4,7 @@ from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac import LiteEthMAC
+from misoclib.com.liteeth.core.mac import LiteEthMAC
 
 from misoclib.com.liteeth.test.common import *
 from misoclib.com.liteeth.test.model import phy, mac

targets/kc705.py

@@ -9,7 +9,7 @@ from misoclib.soc import mem_decoder
 from misoclib.soc.sdram import SDRAMSoC
 
 from misoclib.com.liteeth.phy import LiteEthPHY
-from misoclib.com.liteeth.mac import LiteEthMAC
+from misoclib.com.liteeth.core.mac import LiteEthMAC
 
 
 class _CRG(Module):

targets/mlabs_video.py

@@ -15,7 +15,7 @@ from misoclib.soc import mem_decoder
 from misoclib.soc.sdram import SDRAMSoC
 from misoclib.com import gpio
 from misoclib.com.liteeth.phy import LiteEthPHY
-from misoclib.com.liteeth.mac import LiteEthMAC
+from misoclib.com.liteeth.core.mac import LiteEthMAC
 
 
 class _MXClockPads:

targets/simple.py

@@ -4,7 +4,7 @@ from migen.genlib.io import CRG
 
 from misoclib.soc import SoC, mem_decoder
 from misoclib.com.liteeth.phy import LiteEthPHY
-from misoclib.com.liteeth.mac import LiteEthMAC
+from misoclib.com.liteeth.core.mac import LiteEthMAC
 
 
 class BaseSoC(SoC):