Add RDIMM side-B inversion support
Signed-off-by: David Shah <dave@ds0.me>
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@ -269,6 +269,13 @@ void sdrwlon(void)
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sdram_dfii_pi0_address_write(DDRX_MR1 | (1 << 7));
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sdram_dfii_pi0_address_write(DDRX_MR1 | (1 << 7));
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sdram_dfii_pi0_baddress_write(1);
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sdram_dfii_pi0_baddress_write(1);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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#ifdef SDRAM_PHY_DDR4_RDIMM
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sdram_dfii_pi0_address_write((DDRX_MR1 | (1 << 7)) ^ 0x2BF8) ;
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sdram_dfii_pi0_baddress_write(1 ^ 0xF);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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#endif
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ddrphy_wlevel_en_write(1);
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ddrphy_wlevel_en_write(1);
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}
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}
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@ -277,6 +284,13 @@ void sdrwloff(void)
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sdram_dfii_pi0_address_write(DDRX_MR1);
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sdram_dfii_pi0_address_write(DDRX_MR1);
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sdram_dfii_pi0_baddress_write(1);
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sdram_dfii_pi0_baddress_write(1);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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#ifdef SDRAM_PHY_DDR4_RDIMM
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sdram_dfii_pi0_address_write(DDRX_MR1 ^ 0x2BF8);
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sdram_dfii_pi0_baddress_write(1 ^ 0xF);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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#endif
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ddrphy_wlevel_en_write(0);
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ddrphy_wlevel_en_write(0);
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}
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}
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@ -1158,6 +1172,12 @@ void sdrmrwr(char reg, int value) {
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sdram_dfii_pi0_address_write(value);
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sdram_dfii_pi0_address_write(value);
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sdram_dfii_pi0_baddress_write(reg);
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sdram_dfii_pi0_baddress_write(reg);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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#ifdef SDRAM_PHY_DDR4_RDIMM
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sdram_dfii_pi0_address_write(value ^ 0x2BF8);
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sdram_dfii_pi0_baddress_write(reg ^ 0xF);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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#endif
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}
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}
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static void sdrmpron(char mpr)
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static void sdrmpron(char mpr)
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