Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

gen/fhdl/module: Fix typo.

This commit is contained in:
Florent Kermarrec 2023-02-21 08:26:21 +01:00
parent 22b61c39ca
commit 653b74fe98
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex/gen/fhdl/module.py
View File

@ -40,7 +40,7 @@ class LiteXModule(Module, AutoCSR, AutoDoc):
print(other) print(other)
m.submodules += other m.submodules += other
# - m += special_x equivalent of Migen's m.specials += special_x. # - m += special_x equivalent of Migen's m.specials += special_x.
elif isinstnace(other, Special): elif isinstance(other, Special):
m.specials += other m.specials += other
# - m += cd_x equivalent of Migen's m.clock_domains += cd_x. # - m += cd_x equivalent of Migen's m.clock_domains += cd_x.
elif isinstance(other, ClockDomain): elif isinstance(other, ClockDomain):