cores/cpu: Add KianV CPU (RV32IMA) initial support.
litex_sim --cpu-type=kianv:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2023 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Nov 8 2023 11:14:03
BIOS CRC passed (6984e675)
LiteX git sha1: c1e4b3a8
--=============== SoC ==================--
CPU: KianV-STANDARD @ 1MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128.0KiB
SRAM: 8.0KiB
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> ident
Ident: LiteX Simulation 2023-11-08 11:14:00
litex>
This commit is contained in:
Florent Kermarrec
parent
c1e4b3a850
commit
6598fe9c12
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@ -23,6 +23,7 @@
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- cores/uart : Added 64-bit addressing support to Stream2Wishbone.
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- tools : Added 64-bit addressing support to litex_server/client.
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- cores/cpu : Added 64-bit support to CPUNone.
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- cores/cpu : Added KianV (RV32IMA) initial support.
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[> Changed
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----------
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@ -0,0 +1 @@
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from litex.soc.cores.cpu.kianv.core import KianV
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.section .text, "ax", @progbits
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.global boot_helper
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boot_helper:
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jr x13
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2023 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from litex.gen import *
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
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# Variants -----------------------------------------------------------------------------------------
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CPU_VARIANTS = {
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"standard": "kianv",
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}
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# GCC Flags ----------------------------------------------------------------------------------------
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GCC_FLAGS = {
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# /------------ Base ISA
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# | /------- Hardware Multiply + Divide
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# | |/----- Atomics
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# | ||/---- Compressed ISA
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# | |||/--- Single-Precision Floating-Point
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# | ||||/-- Double-Precision Floating-Point
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# i macfd
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"standard": "-march=rv32i2p0_ma -mabi=ilp32",
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}
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# KianV ------------------------------------------------------------------------------------------
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class KianV(CPU):
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category = "softcore"
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family = "riscv"
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name = "kianv"
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human_name = "kianv"
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variants = CPU_VARIANTS
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data_width = 32
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endianness = "little"
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gcc_triple = CPU_GCC_TRIPLE_RISCV32
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linker_output_format = "elf32-littleriscv"
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nop = "nop"
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io_regions = {0x8000_0000: 0x8000_0000} # Origin, Length.
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# GCC Flags.
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@property
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def gcc_flags(self):
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flags = GCC_FLAGS[self.variant]
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flags += " -D__kianv__ "
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return flags
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def __init__(self, platform, variant="standard"):
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self.platform = platform
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self.variant = variant
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self.human_name = f"KianV-{variant.upper()}"
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self.reset = Signal()
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self.idbus = idbus = wishbone.Interface(data_width=32, address_width=32, addressing="byte")
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self.periph_buses = [idbus] # Peripheral buses (Connected to main SoC's bus).
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self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).
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# KianV Mem Bus.
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# ----------------
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mbus = Record([
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("valid", 1),
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("ready", 1),
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("wstrb", 4),
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("addr", 32),
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("wdata", 32),
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("rdata", 32),
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])
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# KianV Instance.
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# -----------------
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self.cpu_params = dict(
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# Clk / Rst.
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i_clk = ClockSignal("sys"),
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i_resetn = ~(ResetSignal("sys") | self.reset),
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# Parameters.
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p_RESET_ADDR = 0,
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p_STACKADDR = 0,
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p_RV32E = 0,
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# Control/Status.
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o_PC = Open(),
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i_access_fault = 0,
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i_IRQ3 = 0,
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i_IRQ7 = 0,
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# I/D Bus.
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o_mem_valid = mbus.valid,
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i_mem_ready = mbus.ready,
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o_mem_wstrb = mbus.wstrb,
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o_mem_addr = mbus.addr,
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o_mem_wdata = mbus.wdata,
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i_mem_rdata = mbus.rdata,
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)
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# Adapt KianV Mem Bus to Wishbone.
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# --------------------------------
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self.comb += [
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idbus.stb.eq(mbus.valid),
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idbus.cyc.eq(mbus.valid),
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mbus.ready.eq(idbus.ack),
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idbus.we.eq(mbus.wstrb != 0),
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idbus.adr.eq(mbus.addr),
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idbus.sel.eq(mbus.wstrb),
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idbus.dat_w.eq(mbus.wdata),
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mbus.rdata.eq(idbus.dat_r),
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]
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# Add Verilog sources.
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# --------------------
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self.add_sources(platform, variant)
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def set_reset_address(self, reset_address):
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self.reset_address = reset_address
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self.cpu_params.update(p_RESET_ADDR=Constant(reset_address, 32))
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@staticmethod
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def add_sources(platform, variant):
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if not os.path.exists("KianRiscv"):
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os.system(f"git clone https://github.com/splinedrive/kianRiscV")
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vdir = "kianRiscV/linux_socs/kianv_harris_mcycle_edition/kianv_harris_edition"
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platform.add_verilog_include_path(vdir)
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platform.add_source_dir(vdir)
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def do_finalize(self):
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assert hasattr(self, "reset_address")
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self.specials += Instance("kianv_harris_mc_edition", **self.cpu_params)
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@ -0,0 +1,75 @@
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#define MIE_MEIE 0x800
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.global _start
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_start:
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j reset_vector
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reset_vector:
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la sp, _fstack
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la t0, trap_vector
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csrw mtvec, t0
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// initialize .data
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la t0, _fdata
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la t1, _edata
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la t2, _fdata_rom
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1: beq t0, t1, 2f
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lw t3, 0(t2)
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sw t3, 0(t0)
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addi t0, t0, 4
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addi t2, t2, 4
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j 1b
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2:
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// initialize .bss
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la t0, _fbss
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la t1, _ebss
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1: beq t0, t1, 3f
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sw zero, 0(t0)
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addi t0, t0, 4
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j 1b
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3:
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// enable external interrupts
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li t0, MIE_MEIE
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csrs mie, t0
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call main
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1: j 1b
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trap_vector:
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addi sp, sp, -16*4
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sw ra, 0*4(sp)
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sw t0, 1*4(sp)
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sw t1, 2*4(sp)
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sw t2, 3*4(sp)
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sw a0, 4*4(sp)
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sw a1, 5*4(sp)
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sw a2, 6*4(sp)
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sw a3, 7*4(sp)
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sw a4, 8*4(sp)
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sw a5, 9*4(sp)
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sw a6, 10*4(sp)
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sw a7, 11*4(sp)
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sw t3, 12*4(sp)
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sw t4, 13*4(sp)
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sw t5, 14*4(sp)
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sw t6, 15*4(sp)
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call isr
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lw ra, 0*4(sp)
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lw t0, 1*4(sp)
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lw t1, 2*4(sp)
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lw t2, 3*4(sp)
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lw a0, 4*4(sp)
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lw a1, 5*4(sp)
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lw a2, 6*4(sp)
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lw a3, 7*4(sp)
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lw a4, 8*4(sp)
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lw a5, 9*4(sp)
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lw a6, 10*4(sp)
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lw a7, 11*4(sp)
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lw t3, 12*4(sp)
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lw t4, 13*4(sp)
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lw t5, 14*4(sp)
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lw t6, 15*4(sp)
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addi sp, sp, 16*4
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mret
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@ -0,0 +1,4 @@
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#ifndef __IRQ_H
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#define __IRQ_H
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#endif /* __IRQ_H */
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@ -0,0 +1,19 @@
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#ifndef __SYSTEM_H
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#define __SYSTEM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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__attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */
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__attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */
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void flush_l2_cache(void);
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void busy_wait(unsigned int ms);
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void busy_wait_us(unsigned int us);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SYSTEM_H */
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