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soc/interconnect/axi: fix valid signal in connect_to_pads for axi lite

This commit is contained in:
Ilia Sergachev 2021-06-28 11:50:45 +02:00
parent 4d959bbc81
commit 65babd6500
1 changed files with 4 additions and 4 deletions
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8
litex/soc/interconnect/axi.py
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@ -92,10 +92,10 @@ def connect_to_pads(bus, pads, mode="master", axi_full=False):
} }
for channel, mode in channel_modes.items(): for channel, mode in channel_modes.items():
ch = getattr(bus, channel) ch = getattr(bus, channel)
for name, width in ( sig_list = [("valid", 1)] + ch.description.payload_layout
[("valid", 1)] + if ch in ["w", "r"] and axi_full:
[("last", 1)] if (ch in ["w", "r"] and axi_full) else [] + sig_list += [("last", 1)]
ch.description.payload_layout): for name, width in sig_list:
sig = getattr(ch, name) sig = getattr(ch, name)
pad = getattr(pads, channel + name) pad = getattr(pads, channel + name)
if mode == "master": if mode == "master":