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top: connect dvisampler DMA IRQs

This commit is contained in:
Sebastien Bourdeauducq 2013-05-08 22:31:42 +02:00
parent b3d87e1c79
commit 66b4bae7c8
1 changed files with 4 additions and 1 deletions
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5
top.py
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@ -83,6 +83,8 @@ class SoC(Module):
"uart": 0, "uart": 0,
"timer0": 1, "timer0": 1,
"minimac": 2, "minimac": 2,
"dvisampler0": 3,
"dvisampler1": 4,
} }
def __init__(self, platform): def __init__(self, platform):
@ -153,7 +155,8 @@ class SoC(Module):
# Interrupts # Interrupts
# #
for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)): for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq) if hasattr(self, k):
self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
# #
# Clocking # Clocking