top: connect dvisampler DMA IRQs
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parent
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commit
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3
top.py
3
top.py
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@ -83,6 +83,8 @@ class SoC(Module):
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"uart": 0,
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"timer0": 1,
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"minimac": 2,
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"dvisampler0": 3,
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"dvisampler1": 4,
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}
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def __init__(self, platform):
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@ -153,6 +155,7 @@ class SoC(Module):
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# Interrupts
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#
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for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
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if hasattr(self, k):
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self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
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#
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