liteeth: pep8 (E222)

misoclib/com/liteeth/core/etherbone/record.py

@@ -152,7 +152,7 @@ class LiteEthEtherboneRecord(Module):
 
         # receive record, decode it and generate mmap stream
         self.submodules.depacketizer = depacketizer = LiteEthEtherboneRecordDepacketizer()
-        self.submodules.receiver = receiver =  LiteEthEtherboneRecordReceiver()
+        self.submodules.receiver = receiver = LiteEthEtherboneRecordReceiver()
         self.comb += [
             Record.connect(sink, depacketizer.sink),
             Record.connect(depacketizer.source, receiver.sink)
@@ -169,7 +169,7 @@ class LiteEthEtherboneRecord(Module):
         ]
 
         # receive mmap stream, encode it and send records
-        self.submodules.sender = sender =  LiteEthEtherboneRecordSender()
+        self.submodules.sender = sender = LiteEthEtherboneRecordSender()
         self.submodules.packetizer = packetizer = LiteEthEtherboneRecordPacketizer()
         self.comb += [
             Record.connect(sender.source, packetizer.sink),

misoclib/com/liteeth/example_designs/make.py

@@ -75,7 +75,7 @@ if __name__ == "__main__":
     platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
     platform = platform_module.Platform(**platform_kwargs)
 
-    build_name = top_class.__name__.lower() +  "-" + platform_name
+    build_name = top_class.__name__.lower() + "-" + platform_name
     top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
     soc = top_class(platform, **top_kwargs)
     soc.finalize()

misoclib/com/liteeth/generic/depacketizer.py

@@ -80,7 +80,7 @@ class LiteEthDepacketizer(Module):
         fsm.act("COPY",
             sink.ack.eq(source.ack),
             source.stb.eq(sink.stb | no_payload),
-            If(source.stb &  source.ack & source.eop,
+            If(source.stb & source.ack & source.eop,
                 NextState("IDLE")
             )
         )

misoclib/com/liteeth/mac/core/__init__.py

@@ -79,8 +79,8 @@ class LiteEthMACCore(Module, AutoCSR):
         # Cross Domain Crossing
         tx_cdc = AsyncFIFO(eth_phy_description(dw), 64)
         rx_cdc = AsyncFIFO(eth_phy_description(dw), 64)
-        self.submodules +=  RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
-        self.submodules +=  RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
+        self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
+        self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
 
         tx_pipeline += [tx_cdc]
         rx_pipeline += [rx_cdc]