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liteeth: pep8 (E222)

This commit is contained in:
Florent Kermarrec 2015-04-13 10:48:59 +02:00
parent ff2d7f9adc
commit 66ce40d880
4 changed files with 6 additions and 6 deletions
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4
misoclib/com/liteeth/core/etherbone/record.py
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@ -152,7 +152,7 @@ class LiteEthEtherboneRecord(Module):
# receive record, decode it and generate mmap stream # receive record, decode it and generate mmap stream
self.submodules.depacketizer = depacketizer = LiteEthEtherboneRecordDepacketizer() self.submodules.depacketizer = depacketizer = LiteEthEtherboneRecordDepacketizer()
self.submodules.receiver = receiver = LiteEthEtherboneRecordReceiver() self.submodules.receiver = receiver = LiteEthEtherboneRecordReceiver()
self.comb += [ self.comb += [
Record.connect(sink, depacketizer.sink), Record.connect(sink, depacketizer.sink),
Record.connect(depacketizer.source, receiver.sink) Record.connect(depacketizer.source, receiver.sink)
@ -169,7 +169,7 @@ class LiteEthEtherboneRecord(Module):
] ]
# receive mmap stream, encode it and send records # receive mmap stream, encode it and send records
self.submodules.sender = sender = LiteEthEtherboneRecordSender() self.submodules.sender = sender = LiteEthEtherboneRecordSender()
self.submodules.packetizer = packetizer = LiteEthEtherboneRecordPacketizer() self.submodules.packetizer = packetizer = LiteEthEtherboneRecordPacketizer()
self.comb += [ self.comb += [
Record.connect(sender.source, packetizer.sink), Record.connect(sender.source, packetizer.sink),

2
misoclib/com/liteeth/example_designs/make.py
View File

@ -75,7 +75,7 @@ if __name__ == "__main__":
platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option) platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
platform = platform_module.Platform(**platform_kwargs) platform = platform_module.Platform(**platform_kwargs)
build_name = top_class.__name__.lower() + "-" + platform_name build_name = top_class.__name__.lower() + "-" + platform_name
top_kwargs = dict((k, autotype(v)) for k, v in args.target_option) top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
soc = top_class(platform, **top_kwargs) soc = top_class(platform, **top_kwargs)
soc.finalize() soc.finalize()

2
misoclib/com/liteeth/generic/depacketizer.py
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@ -80,7 +80,7 @@ class LiteEthDepacketizer(Module):
fsm.act("COPY", fsm.act("COPY",
sink.ack.eq(source.ack), sink.ack.eq(source.ack),
source.stb.eq(sink.stb | no_payload), source.stb.eq(sink.stb | no_payload),
If(source.stb & source.ack & source.eop, If(source.stb & source.ack & source.eop,
NextState("IDLE") NextState("IDLE")
) )
) )

4
misoclib/com/liteeth/mac/core/__init__.py
View File

@ -79,8 +79,8 @@ class LiteEthMACCore(Module, AutoCSR):
# Cross Domain Crossing # Cross Domain Crossing
tx_cdc = AsyncFIFO(eth_phy_description(dw), 64) tx_cdc = AsyncFIFO(eth_phy_description(dw), 64)
rx_cdc = AsyncFIFO(eth_phy_description(dw), 64) rx_cdc = AsyncFIFO(eth_phy_description(dw), 64)
self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"}) self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"}) self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
tx_pipeline += [tx_cdc] tx_pipeline += [tx_cdc]
rx_pipeline += [rx_cdc] rx_pipeline += [rx_cdc]