soc/interconnect: remove axi_lite
axi_lite code was defining AXI4Lite signals and doing a AXI4Lite bridge to the CSR bus when LiteX was not having proper AXI support. LiteX now has proper AXI support and it also cover what axi_lite was doing: To create a AXILite to CSR bus, user can create an AXILite2Wishbone bridge and then connect the CSR bus directly to the wishbone bus as done in the others non-AXI SoC.
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Florent Kermarrec
parent
745d83a332
commit
67159349d6
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"""AXI4Lite support for LiteX"""
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# Copyright (C) 2018 by Sergiusz Bazanski
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# Permission to use, copy, modify, and/or distribute this software for any
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# purpose with or without fee is hereby granted.
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import math
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from migen import *
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from migen.genlib.record import *
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from litex.soc.interconnect import csr_bus
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# Layout of AXI4 Lite Bus
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_layout = [
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# Write Address
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("aw", [
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("addr", "address_width", DIR_M_TO_S),
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("prot", 3, DIR_M_TO_S),
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("valid", 1, DIR_M_TO_S),
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("ready", 1, DIR_S_TO_M),
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]),
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# Write Data
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("w", [
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("data", "data_width", DIR_M_TO_S),
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("strb", "strb_width", DIR_M_TO_S),
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("valid", 1, DIR_M_TO_S),
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("ready", 1, DIR_S_TO_M),
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]),
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# Write Response
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("b", [
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("resp", 2, DIR_S_TO_M),
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("valid", 1, DIR_S_TO_M),
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("ready", 1, DIR_M_TO_S),
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]),
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# Read Address
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("ar", [
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("addr", "address_width", DIR_M_TO_S),
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("prot", 3, DIR_M_TO_S),
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("valid", 1, DIR_M_TO_S),
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("ready", 1, DIR_S_TO_M),
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]),
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# Read Data
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("r", [
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("data", "data_width", DIR_S_TO_M),
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("resp", 2, DIR_S_TO_M),
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("valid", 1, DIR_S_TO_M),
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("ready", 1, DIR_M_TO_S),
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]),
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]
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class Interface(Record):
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"""AXI4Lite Bus Interface"""
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def __init__(self, data_width=32, address_width=6):
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super().__init__(set_layout_parameters(_layout,
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data_width=data_width,
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address_width=address_width,
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strb_width=data_width//8))
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class AXILite2CSR(Module):
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"""
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A bridge between AXI4Lite and a CSR bus.
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This bridge will let you connect an CSR bus to an AXI4 Lite master. Please
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bear in mind that CSR is word-addressed but AXI4 is byte-addressed. This
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bridge performs translation, so your AXI bus should be at least two bits
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wider then your CSR bus.
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The bridge does not support unaligned reads/writes - it will round down
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every access to the nearest word. If it tries to access unmapped memory,
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it will return whaterver word is currently active on the CSR bus -
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including writes.
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"""
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def __init__(self, bus_axi, bus_csr):
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self.axi = axi = bus_axi
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self.csr = csr = bus_csr
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###
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ar, r, aw, w, b = axi.ar, axi.r, axi.aw, axi.w, axi.b
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# Machine is currently busy talking to CSR, hold your horses.
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busy = Signal()
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# A write transaction is happening on the bus.
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write_transaction = Signal()
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# A read transaction is happening on the bus.
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read_transaction = Signal()
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self.comb += [
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write_transaction.eq(aw.valid & aw.ready & w.valid & w.ready),
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read_transaction.eq(ar.valid & ar.ready),
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]
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# Write transaction generation.
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self.sync += [
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aw.ready.eq(0),
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w.ready.eq(0),
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If(aw.valid & w.valid,
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If(~aw.ready & ~busy & ~ar.valid,
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aw.ready.eq(1),
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w.ready.eq(1)
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)
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)
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]
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# Write response generation.
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self.sync += [
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b.valid.eq(0),
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If(write_transaction,
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If(b.ready & ~b.valid,
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b.valid.eq(1),
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# Response 0 -> OKAY
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b.resp.eq(0),
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)
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)
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]
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# Read transaction generation.
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self.sync += [
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ar.ready.eq(0),
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If(ar.valid & ~ar.ready & ~busy,
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ar.ready.eq(1),
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)
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]
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# Registered data to be written to CSR, set by FSM.
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wdata = Signal(csr.dat_w.nbits)
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# Combinatorial byte address to assert on CSR bus, driven by FSM.
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addr = Signal(ar.addr.nbits)
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# Drive AXI & CSR combinatorial signals.
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self.comb += [
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csr.adr.eq(addr >> int(math.log(r.data.nbits//8, 2.0))),
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csr.dat_w.eq(wdata),
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r.data.eq(csr.dat_r),
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r.resp.eq(0),
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]
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# CSR interaction FSM.
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self.submodules.fsm = fsm = FSM(reset_state='IDLE')
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self.comb += [
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busy.eq(~fsm.ongoing('IDLE')),
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r.valid.eq(fsm.ongoing('READING')),
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csr.we.eq(fsm.ongoing('WRITING')),
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]
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# Idle state - wait for a transaction to happen on AXI. Immediately
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# assert read/write address on CSR if such an transaction is occuring.
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fsm.act('IDLE',
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If(read_transaction,
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addr.eq(ar.addr),
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NextState('READING'),
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).Elif(write_transaction,
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addr.eq(aw.addr),
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# Register data from AXI.
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NextValue(wdata, w.data),
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NextState('WRITING'),
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)
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)
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# Perform write to CSR.
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fsm.act('WRITING',
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addr.eq(aw.addr),
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# CSR writes are single cycle, go back to IDLE.
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NextState('IDLE'),
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)
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# Respond to read to AXI.
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fsm.act('READING',
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addr.eq(ar.addr),
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# If AXI master is ready to receive data, go back to IDLE.
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If(r.ready,
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NextState('IDLE'),
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)
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)
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@ -1,104 +0,0 @@
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import unittest
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from migen import *
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from litex.soc.interconnect import csr
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from litex.soc.interconnect import csr_bus
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from litex.soc.interconnect import axi_lite
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class CSRModule(Module, csr.AutoCSR):
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def __init__(self):
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self.foo = csr.CSRStorage(32, reset=1)
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self.bar = csr.CSRStorage(32, reset=1)
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class AXILiteDUT(Module):
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def __init__(self):
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self.csr = csr_bus.Interface(data_width=32, address_width=12)
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self.axi = axi_lite.Interface(data_width=32, address_width=14)
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self.submodules.csrmodule = CSRModule()
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self.submodules.dut = axi_lite.AXILite2CSR(self.axi, self.csr)
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self.submodules.csrbankarray = csr_bus.CSRBankArray(
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self, self.map_csr, data_width=32, address_width=12)
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self.submodules.csrcon = csr_bus.Interconnect(
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self.csr, self.csrbankarray.get_buses())
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def map_csr(self, name, memory):
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return {"csrmodule": 0}[name]
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class TestAXILite(unittest.TestCase):
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def test_write_read(self):
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def generator(dut):
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axi = dut.axi
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for _ in range(8):
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yield
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# Write test
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yield axi.aw.valid.eq(1)
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yield axi.aw.addr.eq(4)
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yield axi.w.valid.eq(1)
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yield axi.b.ready.eq(1)
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yield axi.w.data.eq(0x2137)
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while (yield axi.aw.ready) != 1:
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yield
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while (yield axi.w.ready) != 1:
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yield
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yield axi.aw.valid.eq(0)
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yield axi.w.valid.eq(0)
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for _ in range(8):
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yield
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# Read test
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yield axi.ar.valid.eq(1)
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yield axi.r.ready.eq(1)
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yield axi.ar.addr.eq(4)
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while (yield axi.ar.ready != 1):
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yield
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yield axi.ar.valid.eq(0)
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while (yield axi.r.valid != 1):
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yield
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yield axi.r.ready.eq(0)
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read = yield axi.r.data
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assert read == 0x2137
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for _ in range(8):
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yield
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dut = AXILiteDUT()
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run_simulation(dut, generator(dut.dut))
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def test_simultaneous(dut):
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def generator(dut):
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axi = dut.axi
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for _ in range(8):
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yield
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# Write
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yield axi.aw.valid.eq(1)
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yield axi.aw.addr.eq(2)
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yield axi.w.valid.eq(1)
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yield axi.b.ready.eq(1)
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yield axi.w.data.eq(0x2137)
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# Read
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yield axi.ar.valid.eq(1)
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yield axi.r.ready.eq(1)
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yield axi.ar.addr.eq(2)
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yield
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yield
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is_reading = yield axi.ar.ready
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is_writing = yield axi.aw.ready
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assert is_reading
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assert not is_writing
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dut = AXILiteDUT()
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run_simulation(dut, generator(dut.dut))
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