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build: always use platform.add_source and avoid manipulate platform.sources directly

This commit is contained in:
Florent Kermarrec 2019-10-17 12:13:06 +02:00
parent 43f5d1ef13
commit 675b455259
4 changed files with 11 additions and 10 deletions
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4
litex/build/lattice/diamond.py
View File

@ -147,8 +147,8 @@ class LatticeDiamondToolchain:
named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v"
v_output.write(v_file)
sources = platform.sources | {(v_file, "verilog", "work")}
_build_files(platform.device, sources, platform.verilog_include_paths, build_name)
platform.add_source(v_file)
_build_files(platform.device, platform.sources, platform.verilog_include_paths, build_name)
tools.write_to_file(build_name + ".lpf", _build_lpf(named_sc, named_pc))

8
litex/build/lattice/icestorm.py
View File

@ -137,13 +137,14 @@ class LatticeIceStormToolchain:
named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v"
v_output.write(v_file)
platform.add_source(v_file)
if use_nextpnr:
chosen_yosys_template = self.nextpnr_yosys_template
else:
chosen_yosys_template = self.yosys_template
ys_contents = "\n".join(_.format(build_name=build_name,
read_files=self.gen_read_files(platform, v_file),
read_files=self.gen_read_files(platform),
synth_opts=synth_opts)
for _ in chosen_yosys_template)
@ -218,13 +219,12 @@ class LatticeIceStormToolchain:
def get_size_string(self, series_size_str):
return series_size_str[2:]
def gen_read_files(self, platform, main):
sources = platform.sources | {(main, "verilog", "work")}
def gen_read_files(self, platform):
incflags = ""
read_files = list()
for path in platform.verilog_include_paths:
incflags += " -I" + path
for filename, language, library in sources:
for filename, language, library in platform.sources:
read_files.append("read_{}{} {}".format(language,
incflags,
filename))

6
litex/build/xilinx/ise.py
View File

@ -202,12 +202,12 @@ class XilinxISEToolchain:
named_sc, named_pc = platform.resolve_signals(vns)
v_file = build_name + ".v"
v_output.write(v_file)
sources = platform.sources | {(v_file, "verilog", "work")}
platform.add_source(v_file)
if mode in ("xst", "cpld"):
_build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt)
_build_xst_files(platform.device, platform.sources, platform.verilog_include_paths, build_name, self.xst_opt)
isemode = mode
else:
_run_yosys(platform.device, sources, platform.verilog_include_paths, build_name)
_run_yosys(platform.device, platform.sources, platform.verilog_include_paths, build_name)
isemode = "edif"
ngdbuild_opt += "-p " + platform.device

3
litex/build/xilinx/vivado.py
View File

@ -253,7 +253,8 @@ class XilinxVivadoToolchain:
named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v"
v_output.write(v_file)
sources = platform.sources | {(v_file, "verilog", "work")}
platform.add_source(v_file)
sources = platform.sources
edifs = platform.edifs
ips = platform.ips
self._build_batch(platform, sources, edifs, ips, build_name, synth_mode, enable_xpm)