build: always use platform.add_source and avoid manipulate platform.sources directly
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parent
43f5d1ef13
commit
675b455259
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@ -147,8 +147,8 @@ class LatticeDiamondToolchain:
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named_sc, named_pc = platform.resolve_signals(v_output.ns)
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v_file = build_name + ".v"
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v_output.write(v_file)
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sources = platform.sources | {(v_file, "verilog", "work")}
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_build_files(platform.device, sources, platform.verilog_include_paths, build_name)
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platform.add_source(v_file)
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_build_files(platform.device, platform.sources, platform.verilog_include_paths, build_name)
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tools.write_to_file(build_name + ".lpf", _build_lpf(named_sc, named_pc))
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@ -137,13 +137,14 @@ class LatticeIceStormToolchain:
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named_sc, named_pc = platform.resolve_signals(v_output.ns)
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v_file = build_name + ".v"
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v_output.write(v_file)
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platform.add_source(v_file)
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if use_nextpnr:
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chosen_yosys_template = self.nextpnr_yosys_template
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else:
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chosen_yosys_template = self.yosys_template
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ys_contents = "\n".join(_.format(build_name=build_name,
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read_files=self.gen_read_files(platform, v_file),
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read_files=self.gen_read_files(platform),
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synth_opts=synth_opts)
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for _ in chosen_yosys_template)
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@ -218,13 +219,12 @@ class LatticeIceStormToolchain:
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def get_size_string(self, series_size_str):
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return series_size_str[2:]
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def gen_read_files(self, platform, main):
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sources = platform.sources | {(main, "verilog", "work")}
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def gen_read_files(self, platform):
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incflags = ""
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read_files = list()
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for path in platform.verilog_include_paths:
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incflags += " -I" + path
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for filename, language, library in sources:
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for filename, language, library in platform.sources:
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read_files.append("read_{}{} {}".format(language,
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incflags,
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filename))
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@ -202,12 +202,12 @@ class XilinxISEToolchain:
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named_sc, named_pc = platform.resolve_signals(vns)
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v_file = build_name + ".v"
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v_output.write(v_file)
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sources = platform.sources | {(v_file, "verilog", "work")}
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platform.add_source(v_file)
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if mode in ("xst", "cpld"):
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_build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt)
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_build_xst_files(platform.device, platform.sources, platform.verilog_include_paths, build_name, self.xst_opt)
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isemode = mode
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else:
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_run_yosys(platform.device, sources, platform.verilog_include_paths, build_name)
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_run_yosys(platform.device, platform.sources, platform.verilog_include_paths, build_name)
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isemode = "edif"
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ngdbuild_opt += "-p " + platform.device
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@ -253,7 +253,8 @@ class XilinxVivadoToolchain:
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named_sc, named_pc = platform.resolve_signals(v_output.ns)
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v_file = build_name + ".v"
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v_output.write(v_file)
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sources = platform.sources | {(v_file, "verilog", "work")}
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platform.add_source(v_file)
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sources = platform.sources
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edifs = platform.edifs
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ips = platform.ips
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self._build_batch(platform, sources, edifs, ips, build_name, synth_mode, enable_xpm)
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