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fhdl: support memory read enable

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This commit is contained in:
Sebastien Bourdeauducq 2012-01-27 21:39:23 +01:00
parent 0cc7e2ac1e
commit 685b5eb08f
2 changed files with 14 additions and 7 deletions
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8
examples/memory.py
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@ -9,13 +9,15 @@ a1 = Signal(BV(d_b))
d1 = Signal(BV(w)) d1 = Signal(BV(w))
we1 = Signal(BV(4)) we1 = Signal(BV(4))
dw1 = Signal(BV(w)) dw1 = Signal(BV(w))
p1 = MemoryPort(a1, d1, we1, dw1, we_granularity=8, mode=WRITE_FIRST) re = Signal()
p1 = MemoryPort(a1, d1, we1, dw1, we_granularity=8)
a2 = Signal(BV(d_b)) a2 = Signal(BV(d_b))
d2 = Signal(BV(w)) d2 = Signal(BV(w))
p2 = MemoryPort(a2, d2) re2 = Signal()
p2 = MemoryPort(a2, d2, re=re2)
mem = Memory(w, d, p1, p2, init=[5, 18, 32]) mem = Memory(w, d, p1, p2, init=[5, 18, 32])
f = Fragment(memories=[mem]) f = Fragment(memories=[mem])
v = verilog.convert(f, ios={a1, d1, we1, dw1, a2, d2}) v = verilog.convert(f, ios={a1, d1, we1, dw1, a2, d2, re2})
print(v) print(v)

13
migen/fhdl/verilog_mem_behavioral.py
View file

@ -41,14 +41,19 @@ def handler(memory, ns, clk):
r += "\t\t" + gn(storage) + "[" + gn(port.adr) + "] <= " + gn(port.dat_w) + ";\n" r += "\t\t" + gn(storage) + "[" + gn(port.adr) + "] <= " + gn(port.dat_w) + ";\n"
if not port.async_read: if not port.async_read:
if port.mode == WRITE_FIRST and port.we is not None: if port.mode == WRITE_FIRST and port.we is not None:
r += "\t" + gn(adr_regs[id(port)]) + " <= " + gn(port.adr) + ";\n" rd = "\t" + gn(adr_regs[id(port)]) + " <= " + gn(port.adr) + ";\n"
else: else:
bassign = gn(data_regs[id(port)]) + " <= " + gn(storage) + "[" + gn(port.adr) + "];\n" bassign = gn(data_regs[id(port)]) + " <= " + gn(storage) + "[" + gn(port.adr) + "];\n"
if port.mode == READ_FIRST or port.we is None: if port.mode == READ_FIRST or port.we is None:
r += "\t" + bassign rd = "\t" + bassign
elif port.mode == NO_CHANGE: elif port.mode == NO_CHANGE:
r += "\tif (!" + gn(port.we) + ")\n" rd = "\tif (!" + gn(port.we) + ")\n" \
r += "\t\t" + bassign + "\t\t" + bassign
if port.re is None:
r += rd
else:
r += "\tif (" + gn(port.re) + ")\n"
r += "\t" + rd.replace("\n\t", "\n\t\t")
r += "end\n\n" r += "end\n\n"
for port in memory.ports: for port in memory.ports: