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soc/cores/clock: change drp_locked to CSRStatus and connect it :)

This commit is contained in:
Florent Kermarrec 2019-11-20 19:36:51 +01:00
parent 36107cdfd7
commit 6883a43680
1 changed files with 9 additions and 8 deletions
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17
litex/soc/cores/clock.py
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@ -91,14 +91,14 @@ class XilinxClocking(Module, AutoCSR):
raise ValueError("No PLL config found") raise ValueError("No PLL config found")
def expose_drp(self): def expose_drp(self):
self.drp_reset = CSR() self.drp_reset = CSR()
self.drp_locked = CSR() self.drp_locked = CSRStatus()
self.drp_read = CSR() self.drp_read = CSR()
self.drp_write = CSR() self.drp_write = CSR()
self.drp_drdy = CSRStatus() self.drp_drdy = CSRStatus()
self.drp_adr = CSRStorage(7) self.drp_adr = CSRStorage(7)
self.drp_dat_w = CSRStorage(16) self.drp_dat_w = CSRStorage(16)
self.drp_dat_r = CSRStatus(16) self.drp_dat_r = CSRStatus(16)
# # # # # #
@ -119,6 +119,7 @@ class XilinxClocking(Module, AutoCSR):
self.drp_drdy.status.eq(1) self.drp_drdy.status.eq(1)
) )
] ]
self.comb += self.drp_locked.status.eq(self.locked)
def do_finalize(self): def do_finalize(self):
assert hasattr(self, "clkin") assert hasattr(self, "clkin")