Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #789 from antmicro/jboc/litex-sim-fix-name 

litex_sim: fix old name: get_cl_cw -> get_default_cl_cwl
This commit is contained in:
enjoy-digital 2021-01-29 19:13:34 +01:00 committed by GitHub
parent 2287f73937 61e605da92
commit 69307cfdde
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litex/tools/litex_sim.py
View File

@ -114,7 +114,7 @@ def get_sdram_phy_settings(memtype, data_width, clk_freq):
elif memtype in ["DDR2", "DDR3"]: elif memtype in ["DDR2", "DDR3"]:
# Settings from s7ddrphy # Settings from s7ddrphy
tck = 2/(2*nphases*clk_freq) tck = 2/(2*nphases*clk_freq)
cl, cwl = get_cl_cw(memtype, tck) cl, cwl = get_default_cl_cwl(memtype, tck)
cl_sys_latency = get_sys_latency(nphases, cl) cl_sys_latency = get_sys_latency(nphases, cl)
cwl_sys_latency = get_sys_latency(nphases, cwl) cwl_sys_latency = get_sys_latency(nphases, cwl)
rdphase = get_sys_phase(nphases, cl_sys_latency, cl) rdphase = get_sys_phase(nphases, cl_sys_latency, cl)
@ -124,7 +124,7 @@ def get_sdram_phy_settings(memtype, data_width, clk_freq):
elif memtype == "DDR4": elif memtype == "DDR4":
# Settings from usddrphy # Settings from usddrphy
tck = 2/(2*nphases*clk_freq) tck = 2/(2*nphases*clk_freq)
cl, cwl = get_cl_cw(memtype, tck) cl, cwl = get_default_cl_cwl(memtype, tck)
cl_sys_latency = get_sys_latency(nphases, cl) cl_sys_latency = get_sys_latency(nphases, cl)
cwl_sys_latency = get_sys_latency(nphases, cwl) cwl_sys_latency = get_sys_latency(nphases, cwl)
rdphase = get_sys_phase(nphases, cl_sys_latency, cl) rdphase = get_sys_phase(nphases, cl_sys_latency, cl)