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integration/soc/add_ethernet/etherbone: Add with_timing_constraints parameter to allow disabling constraints. 

Some boards require specific constraints, so disable them in this case and put constraints in the target file.
This commit is contained in:
Florent Kermarrec 2021-09-13 19:32:50 +02:00
parent cb7b0f44cf
commit 694878a35a
1 changed files with 25 additions and 21 deletions
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46
litex/soc/integration/soc.py
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@ -1397,9 +1397,10 @@ class LiteXSoC(SoC):
# Add Ethernet --------------------------------------------------------------------------------- # Add Ethernet ---------------------------------------------------------------------------------
def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth", dynamic_ip=False, software_debug=False, def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth", dynamic_ip=False, software_debug=False,
nrxslots = 2, nrxslots = 2,
ntxslots = 2, ntxslots = 2,
with_timestamp = False): with_timestamp = False,
with_timing_constraints = True):
# Imports # Imports
from liteeth.mac import LiteEthMAC from liteeth.mac import LiteEthMAC
from liteeth.phy.model import LiteEthPHYModel from liteeth.phy.model import LiteEthPHYModel
@ -1430,14 +1431,6 @@ class LiteXSoC(SoC):
if self.irq.enabled: if self.irq.enabled:
self.irq.add(name, use_loc_if_exists=True) self.irq.add(name, use_loc_if_exists=True)
# Timing constraints
eth_rx_clk = getattr(phy, "crg", phy).cd_eth_rx.clk
eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk
if not isinstance(phy, LiteEthPHYModel):
self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
# Dynamic IP (if enabled). # Dynamic IP (if enabled).
if dynamic_ip: if dynamic_ip:
self.add_constant("ETH_DYNAMIC_IP") self.add_constant("ETH_DYNAMIC_IP")
@ -1447,12 +1440,22 @@ class LiteXSoC(SoC):
self.add_constant("ETH_UDP_TX_DEBUG") self.add_constant("ETH_UDP_TX_DEBUG")
self.add_constant("ETH_UDP_RX_DEBUG") self.add_constant("ETH_UDP_RX_DEBUG")
# Timing constraints
if with_timing_constraints:
eth_rx_clk = getattr(phy, "crg", phy).cd_eth_rx.clk
eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk
if not isinstance(phy, LiteEthPHYModel):
self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
# Add Etherbone -------------------------------------------------------------------------------- # Add Etherbone --------------------------------------------------------------------------------
def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth", def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth",
mac_address = 0x10e2d5000000, mac_address = 0x10e2d5000000,
ip_address = "192.168.1.50", ip_address = "192.168.1.50",
udp_port = 1234, udp_port = 1234,
buffer_depth = 4): buffer_depth = 4,
with_timing_constraints = True):
# Imports # Imports
from liteeth.core import LiteEthUDPIPCore from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone from liteeth.frontend.etherbone import LiteEthEtherbone
@ -1483,12 +1486,13 @@ class LiteXSoC(SoC):
self.add_wb_master(etherbone.wishbone.bus) self.add_wb_master(etherbone.wishbone.bus)
# Timing constraints # Timing constraints
eth_rx_clk = getattr(phy, "crg", phy).cd_eth_rx.clk if with_timing_constraints:
eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk eth_rx_clk = getattr(phy, "crg", phy).cd_eth_rx.clk
if not isinstance(phy, LiteEthPHYModel): eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk
self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq) if not isinstance(phy, LiteEthPHYModel):
self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq) self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk) self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
# Add SPI Flash -------------------------------------------------------------------------------- # Add SPI Flash --------------------------------------------------------------------------------
def add_spi_flash(self, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None, module=None, phy=None, rate="1:1", **kwargs): def add_spi_flash(self, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None, module=None, phy=None, rate="1:1", **kwargs):