cpu/zynq7000: correct address map
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@ -23,17 +23,20 @@ class Zynq7000(CPU):
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human_name = "Zynq7000"
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human_name = "Zynq7000"
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data_width = 32
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data_width = 32
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endianness = "little"
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endianness = "little"
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reset_address = 0x00000000
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reset_address = 0xfc00_0000
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gcc_triple = "arm-none-eabi"
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gcc_triple = "arm-none-eabi"
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gcc_flags = "-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard"
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gcc_flags = "-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard"
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linker_output_format = "elf32-littlearm"
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linker_output_format = "elf32-littlearm"
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nop = "nop"
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nop = "nop"
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io_regions = {0x00000000: 0x100000000} # Origin, Length.
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io_regions = {0x4000_0000: 0xbc00_0000} # Origin, Length.
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# Memory Mapping.
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# Memory Mapping.
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@property
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@property
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def mem_map(self):
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def mem_map(self):
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return {"csr": 0x00000000}
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return {
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"sram": 0x10_0000, # DDR in fact
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"rom": 0xfc00_0000,
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}
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def __init__(self, platform, variant, *args, **kwargs):
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def __init__(self, platform, variant, *args, **kwargs):
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super().__init__(*args, **kwargs)
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super().__init__(*args, **kwargs)
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