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build/xilinx/vivado: use build_name as top in synth_design

This commit is contained in:
Florent Kermarrec 2015-12-09 11:40:27 +01:00
parent 3191533889
commit 6a4e3bb5c0
1 changed files with 1 additions and 1 deletions
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2
litex/build/xilinx/vivado.py
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@ -87,7 +87,7 @@ class XilinxVivadoToolchain:
tcl.append("read_xdc {}.xdc".format(build_name)) tcl.append("read_xdc {}.xdc".format(build_name))
tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands) tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
tcl.append("synth_design -top top -part {} -include_dirs {{{}}}".format(platform.device, " ".join(platform.verilog_include_paths))) tcl.append("synth_design -top {} -part {} -include_dirs {{{}}}".format(build_name, platform.device, " ".join(platform.verilog_include_paths)))
tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name)) tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name))
tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name)) tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name))
tcl.append("place_design") tcl.append("place_design")