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Merge pull request #24 from mithro/vivado-mor1k-fix 

vivado: Fix segfault with or1k.
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enjoy-digital 2017-05-04 15:09:00 +02:00 committed by GitHub
parent bedd428d9d 5f9ff09c08
commit 6a7604cbb0
1 changed files with 5 additions and 1 deletions
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6
litex/build/xilinx/vivado.py
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@ -97,7 +97,11 @@ class XilinxVivadoToolchain:
tcl.append("read_xdc {}.xdc".format(build_name)) tcl.append("read_xdc {}.xdc".format(build_name))
tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands) tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
tcl.append("synth_design -top {} -part {} -include_dirs {{{}}}".format(build_name, platform.device, " ".join(platform.verilog_include_paths))) if platform.verilog_include_paths:
synth_design_extra = "-include_dirs {{{}}}".format(" ".join(platform.verilog_include_paths))
else:
synth_design_extra = ""
tcl.append("synth_design -top {} -part {} {}".format(build_name, platform.device, synth_design_extra))
tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name)) tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(build_name))
tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name)) tcl.append("report_utilization -file {}_utilization_synth.rpt".format(build_name))
tcl.append("place_design") tcl.append("place_design")