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cores/uart/UARTCrossover: increase rx_fifo_depth to allow speeding up litex_term.

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This commit is contained in:
Florent Kermarrec 2021-02-18 17:55:53 +01:00
parent fc83a9281a
commit 6ac410a462
1 changed files with 1 additions and 1 deletions
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2
litex/soc/cores/uart.py
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@ -444,7 +444,7 @@ class UARTCrossover(UART):
def __init__(self, **kwargs):
assert kwargs.get("phy", None) == None
UART.__init__(self, **kwargs)
self.submodules.xover = UART(tx_fifo_depth=1, rx_fifo_depth=1, rx_fifo_rx_we=True)
self.submodules.xover = UART(tx_fifo_depth=1, rx_fifo_depth=16, rx_fifo_rx_we=True)
self.comb += [
self.source.connect(self.xover.sink),
self.xover.source.connect(self.sink)