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cores/dma: Don’t drop data while idle.

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Vegard Storheil Eriksen 2022-09-10 10:13:18 +02:00
parent 15f72174ce
commit 6ad6d1e414
1 changed files with 0 additions and 1 deletions
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litex/soc/cores/dma.py
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@ -182,7 +182,6 @@ class WishboneDMAWriter(Module, AutoCSR):
self.submodules += fsm self.submodules += fsm
self.comb += fsm.reset.eq(~self._enable.storage) self.comb += fsm.reset.eq(~self._enable.storage)
fsm.act("IDLE", fsm.act("IDLE",
self.sink.ready.eq(1),
NextValue(offset, 0), NextValue(offset, 0),
NextState("RUN"), NextState("RUN"),
) )