boards: keep in sync with litex-boards.

litex/boards/platforms/arty.py

@@ -145,6 +145,25 @@ _io = [
     ),
 ]
 
+_i2s_pmod_io = [
+    # I2S PMOD on JD:
+    # - https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/
+    ("i2s_rx_mclk", 0, Pins("E2"), IOStandard("LVCMOS33")),
+    ("i2s_rx", 0,
+        Subsignal("clk", Pins("H2")),
+        Subsignal("sync", Pins("D2")),
+        Subsignal("rx", Pins("G2")),
+        IOStandard("LVCMOS33"),
+    ),
+    ("i2s_tx_mclk", 0, Pins("D4"), IOStandard("LVCMOS33")),
+    ("i2s_tx", 0,
+        Subsignal("clk",Pins("F4")),
+        Subsignal("sync", Pins("D3")),
+        Subsignal("tx", Pins("F3")),
+        IOStandard("LVCMOS33"),
+    ),
+]
+
 _sdcard_pmod_io = [
     # SDCard PMOD on JD:
     # - https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
@@ -158,8 +177,8 @@ _sdcard_pmod_io = [
         IOStandard("LVCMOS33"),
     ),
     ("sdcard", 0,
-        Subsignal("data", Pins("F4 E2 D2 D4")),
+        Subsignal("data", Pins("F4 E2 D2 D4"), Misc("PULLUP True")),
-        Subsignal("cmd", Pins("D3")),
+        Subsignal("cmd", Pins("D3"), Misc("PULLUP True")),
         Subsignal("clk", Pins("F3")),
         Subsignal("cd", Pins("H2")),
         Misc("SLEW=FAST"),

litex/boards/platforms/genesys2.py

@@ -145,6 +145,7 @@ class Platform(XilinxPlatform):
 
     def __init__(self):
         XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
+        self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
 
     def create_programmer(self):
         return OpenOCD("openocd_genesys2.cfg", "bscan_spi_xc7a325t.bit")

litex/boards/platforms/kc705.py

@@ -448,6 +448,10 @@ _connectors = [
     ("LPC", {
         "GBTCLK0_M2C_P" : "N8",
         "GBTCLK0_M2C_N" : "N7",
+        "DP0_C2M_P"     : "F2",
+        "DP0_C2M_N"     : "F1",
+        "DP0_M2C_P"     : "F6",
+        "DP0_M2C_N"     : "F5",
         "LA01_CC_P"     : "AE23",
         "LA01_CC_N"     : "AF23",
         "LA05_P"        : "AG22",

litex/boards/platforms/ulx3s.py

@@ -38,7 +38,8 @@ _io = [
         Subsignal("clk",  Pins("J1")),
         Subsignal("cmd",  Pins("J3"), Misc("PULLMODE=UP")),
         Subsignal("data", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
-        IOStandard("LVCMOS33"), Misc("SLEW=FAST")
+        Misc("SLEWRATE=FAST"),
+        IOStandard("LVCMOS33"),
     ),
 
     ("sdram_clock", 0, Pins("F19"),
@@ -108,6 +109,7 @@ class Platform(LatticePlatform):
     default_clk_period = 1e9/25e6
 
     def __init__(self, device="LFE5U-45F", **kwargs):
+        assert device in ["LFE5U-25F", "LFE5U-45F", "LFE5U-85F"]
         LatticePlatform.__init__(self, device + "-6BG381C", _io, **kwargs)
 
     def create_programmer(self):

litex/boards/targets/minispartan6.py

@@ -23,29 +23,38 @@ from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
 from litedram.modules import AS4C16M16
-from litedram.phy import GENSDRPHY
+from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
 
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
-    def __init__(self, platform, clk_freq):
+    def __init__(self, platform, clk_freq, sdram_sys2x=False):
         self.clock_domains.cd_sys    = ClockDomain()
-        self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
+        if sdram_sys2x:
+            self.clock_domains.cd_sys2x = ClockDomain()
+            self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
+        else:
+            self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
 
         # # #
 
         self.submodules.pll = pll = S6PLL(speedgrade=-1)
         pll.register_clkin(platform.request("clk32"), 32e6)
         pll.create_clkout(self.cd_sys,    clk_freq)
-        pll.create_clkout(self.cd_sys_ps, clk_freq, phase=90)
+        if sdram_sys2x:
+            pll.create_clkout(self.cd_sys2x, 2*clk_freq)
+            pll.create_clkout(self.cd_sys2x_ps, 2*clk_freq, phase=90)
+        else:
+            pll.create_clkout(self.cd_sys_ps, clk_freq, phase=90)
 
         # SDRAM clock
-        self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
+        sdram_clk = ClockSignal("sys2x_ps" if sdram_sys2x else "sys_ps")
+        self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
 
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(80e6), **kwargs):
+    def __init__(self, sys_clk_freq=int(80e6), sdram_sys2x=False, **kwargs):
         platform = minispartan6.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -55,14 +64,19 @@ class BaseSoC(SoCCore):
             **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
-        self.submodules.crg = _CRG(platform, sys_clk_freq)
+        self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_sys2x=sdram_sys2x)
 
         # SDR SDRAM --------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
-            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
+            if sdram_sys2x:
+                self.submodules.sdrphy = HalfRateGENSDRPHY(platform.request("sdram"))
+                rate = "1:2"
+            else:
+                self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
+                rate = "1:1"
             self.add_sdram("sdram",
                 phy                     = self.sdrphy,
-                module                  = AS4C16M16(sys_clk_freq, "1:1"),
+                module                  = AS4C16M16(sys_clk_freq, rate),
                 origin                  = self.mem_map["main_ram"],
                 size                    = kwargs.get("max_sdram_size", 0x40000000),
                 l2_cache_size           = kwargs.get("l2_size", 8192),
@@ -80,13 +94,14 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on MiniSpartan6")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--build",        action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    parser.add_argument("--load",         action="store_true", help="Load bitstream")
+    parser.add_argument("--sdram-sys2x",  action="store_true", help="Use double frequency for SDRAM PHY")
     builder_args(parser)
     soc_sdram_args(parser)
     args = parser.parse_args()
 
-    soc = BaseSoC(**soc_sdram_argdict(args))
+    soc = BaseSoC(sdram_sys2x=args.sdram_sys2x, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)