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cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq

This commit is contained in:
Florent Kermarrec 2019-08-07 08:17:44 +02:00
parent 1884649de1
commit 6b7ca0cff7
1 changed files with 1 additions and 1 deletions
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litex/soc/cores/clock.py
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@ -64,7 +64,7 @@ class XilinxClocking(Module, AutoCSR):
config = {} config = {}
for divclk_divide in range(*self.divclk_divide_range): for divclk_divide in range(*self.divclk_divide_range):
config["divclk_divide"] = divclk_divide config["divclk_divide"] = divclk_divide
for clkfbout_mult in range(*self.clkfbout_mult_frange): for clkfbout_mult in reversed(range(*self.clkfbout_mult_frange)):
all_valid = True all_valid = True
vco_freq = self.clkin_freq*clkfbout_mult/divclk_divide vco_freq = self.clkin_freq*clkfbout_mult/divclk_divide
(vco_freq_min, vco_freq_max) = self.vco_freq_range (vco_freq_min, vco_freq_max) = self.vco_freq_range