Wip de0_nano example
This commit is contained in:
Florent Kermarrec
parent
1578c74895
commit
6b8dda03c6
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@ -9,8 +9,8 @@ build/soc.qsf:
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$(PYTHON) build.py
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build/soc.map: build/soc.qsf
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cp soc.qpf build/soc.qpf
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cd build && quartus_map soc.qpf
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cp soc.qpf build/de0_nano.qpf
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cd build && quartus_map de0_nano.qpf
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clean:
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rm -rf build/*
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@ -19,15 +19,6 @@ def get_qsf_prj():
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r += "set_global_assignment -name VERILOG_FILE " + s + "\n"
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return r
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add_core_dir("generic")
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add_core_dir("lm32")
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add_core_dir("hpdmc_sdr16")
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add_core_dir("fmlbrg")
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add_core_dir("uart")
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add_core_dir("rc5")
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add_core_dir("gpio")
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add_core_dir("spi_master")
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os.chdir("build")
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def str2file(filename, contents):
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@ -37,8 +28,8 @@ def str2file(filename, contents):
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# generate top
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(src_verilog, qsf_cst) = top.get()
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str2file("soc.v", src_verilog)
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verilog_sources.append("build/soc.v")
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str2file("de0_nano.v", src_verilog)
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verilog_sources.append("build/de0_nano.v")
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# generate Quartus project file
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qsf_prj = get_qsf_prj()
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@ -1,5 +1,5 @@
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class Constraints:
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def __init__(self, uart0, rc50, gpio0, led0, sw0, spi_master0, hpdmc0):
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def __init__(self):
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self.constraints = []
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def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""):
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self.constraints.append((signal, vec, pin, iostandard, extra,sch))
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@ -10,50 +10,6 @@ class Constraints:
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add(signal, p, i, iostandard, extra)
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i += 1
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# uart0
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#add(uart0.tx, "TBD")
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#add(uart0.rx, "TBD")
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# rc50
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#add(rc50.rx, "TBD")
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# gpio0
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#add_vec(gpio0.inputs, ["TBD","TBD","TBD","TBD",
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# "TBD","TBD","TBD","TBD"])
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#add_vec(gpio0.outputs, ["TBD","TBD","TBD","TBD",
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# "TBD","TBD","TBD","TBD"])
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# led0
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add_vec(led0.outputs, ["A15", "A13", "B13", "A11",
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"D1" , "F3" , "B1" , "L3"])
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# sw0
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add_vec(sw0.inputs, ["M1", "T8", "B9", "M15"])
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# spi_master0
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add(spi_master0.cs, "TBD")
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add(spi_master0.sck, "TBD")
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add(spi_master0.mosi, "TBD")
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add(spi_master0.miso, "TBD")
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# hpdmc0
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add(hpdmc0.sdram_clk, "R4")
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add(hpdmc0.sdram_cke, "L7")
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add(hpdmc0.sdram_cs_n, "P6")
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add(hpdmc0.sdram_we_n, "C2")
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add(hpdmc0.sdram_cas_n, "L1")
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add(hpdmc0.sdram_ras_n, "L2")
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add_vec(hpdmc0.sdram_addr, ["P2","N5","N6","M8",
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"P8","T7","N8","T6",
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"R1","P1","N2","N1",
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"L4",])
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add_vec(hpdmc0.sdram_ba, ["M7","M6"])
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add_vec(hpdmc0.sdram_dqm, ["R6","T5"])
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add_vec(hpdmc0.sdram_dq, ["G2", "G1", "L8", "K5",
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"K2", "J2", "J1", "R7",
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"T4", "T2", "T3", "R3",
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"R5", "P3", "N3", "K1"])
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def get_ios(self):
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return set([c[0] for c in self.constraints])
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@ -1,24 +1,50 @@
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# De0Nano-System On Chip / Generic Base for a Custom SOC
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# - Lm32 SoftCore
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# - 32MB Sdram
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# - 2KB Eeprom (TBD)
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# - G Sensor & AD Converter (TBD)
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# - Up to 72 GPIO (8 in/ 8 out)
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# - Uart
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# - Spi Slave & Master (Only Master)
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################################################################################
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# _____ _ ____ _ _ _ _
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# | __|___ |_|___ _ _ | \|_|___|_| |_ ___| |
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# | __| | | | . | | | | | | | . | | _| .'| |
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# |_____|_|_|_| |___|_ | |____/|_|_ |_|_| |__,|_|
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# |___| |___| |___|
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#
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# Copyright 2012 / Florent Kermarrec / florent@enjoy-digital.fr
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#
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# migScope Example on De0 Nano Board
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# ----------------------------------
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################################################################################
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#
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# In this example, signals are generated inside generated inside the FPGA.
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# We will use migScope to record those signals it and visualize them.
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#
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# Example architecture:
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# ----------------------
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# migScope Config <-- Python Client (Host) --> Vcd Output
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# |
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# Arduino (Uart<-->Spi Bridge)
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# |
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# De0 Nano
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# |
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# +--------------------+-----------------------+
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# migIo Signal Generator migLa
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# Control of Signal Ramp, Sinus, Logic Analyzer
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# generator Square, ...
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###############################################################################
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#==============================================================================
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# I M P O R T
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#==============================================================================
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from fractions import Fraction
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from math import ceil
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from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import wishbone, csr, wishbone2csr, fml
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from migen.bus import csr
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from migen.bus.transactions import *
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from migen.bank import description, csrgen
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from migen.bank.description import *
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import sys
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sys.path.append("../../")
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from migScope import trigger, recorder
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import spi2Csr
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from soc import lm32, uart, rc5, gpio, spi_master, identifier, fmlbrg, hpdmc_sdr16
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from cmacros import get_macros
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from timings import *
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from constraints import Constraints
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@ -31,93 +57,74 @@ clk_freq = 50*MHz
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clk_period_ns = clk_freq*ns
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n = t2n(clk_period_ns)
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# Bus Width
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trig_width = 16
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dat_width = 16
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# Record Size
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record_size = 1024
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# Csr Addr
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CONTROL_ADDR = 0x0000
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TRIGGER_ADDR = 0x0200
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RECORDER_ADDR = 0x0400
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#==============================================================================
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# S O C
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# M I S C O P E E X A M P L E
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#==============================================================================
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#
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# Configuration
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#===============================================================================
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# Csr
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csr_macros = get_macros("common/csrbase.h")
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def csr_offset(name):
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base = int(csr_macros[name + "_BASE"], 0)
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assert((base >= 0xe0000000) and (base <= 0xe0010000))
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return (base - 0xe0000000)//0x800
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# Interrupt
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interrupt_macros = get_macros("common/interrupt.h")
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def interrupt_n(name):
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return int(interrupt_macros[name + "_INTERRUPT"], 0)
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# Version
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version = get_macros("common/version.h")["VERSION"][1:-1]
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def get():
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#
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# Wishbone
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#===============================================================================
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cpu0 = lm32.LM32()
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wishbone2csr0 = wishbone2csr.WB2CSR()
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fmlbrg0 = fmlbrg.FMLBRG(16)
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hpdmc0 = hpdmc_sdr16.HPDMC_SDR16(13)
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# Control Reg
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control_reg0 = RegisterField("control_reg0", 32, reset=0, access_dev=READ_ONLY)
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regs = [control_reg0]
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bank0 = csrgen.Bank(regs,address=CONTROL_ADDR)
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# CSR 0x00000000 (shadow @0x80000000)
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# FML bridge 0x10000000 (shadow @0x90000000)
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wishbonecon = wishbone.InterconnectShared(
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# Trigger
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term0 = trigger.Term(trig_width)
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trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0])
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# Recorder
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recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size)
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# Spi2Csr
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spi2csr0 = spi2Csr.Spi2Csr(16,8)
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# Csr Interconnect
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csrcon0 = csr.Interconnect(spi2csr0.csr,
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[
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cpu0.ibus,
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cpu0.dbus
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], [
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(binc("000") , wishbone2csr0.wishbone),
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(binc("001") , fmlbrg0.wishbone)
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],
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register=True,
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offset=1)
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#
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# Fml
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#===============================================================================
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fmlcon0 = fml.Interconnect(fmlbrg0.fml,hpdmc0.fml)
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#
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# Csr
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#===============================================================================
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uart0 = uart.UART(csr_offset("UART"), clk_freq, baud=115200)
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identifier0 = identifier.Identifier(csr_offset("ID"), 0x1234, version, int(clk_freq))
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rc50 = rc5.RC5(csr_offset("RC5"),clk_freq)
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gpio0 = gpio.GPIO(csr_offset("GPIO"))
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led0 = gpio.GPIO(csr_offset("LED"))
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sw0 = gpio.GPIO(csr_offset("SW"),4)
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spi_master0 = spi_master.SPI_MASTER(csr_offset("SPI_MASTER"))
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csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
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uart0.csr,
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identifier0.bank.interface,
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rc50.csr,
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gpio0.csr,
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led0.csr,
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sw0.csr,
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spi_master0.csr,
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hpdmc0.csr
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bank0.interface,
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trigger0.bank.interface,
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recorder0.bank.interface
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])
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comb = []
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sync = []
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# Signal Generator
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sig_gen = Signal(BV(trig_width))
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sync += [
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sig_gen.eq(sig_gen+1)
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]
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# Dat / Trig Bus
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comb += [
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trigger0.in_trig.eq(sig_gen),
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trigger0.in_dat.eq(sig_gen)
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]
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# Trigger --> Recorder
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comb += [
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recorder0.trig_dat.eq(trigger0.dat),
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recorder0.trig_hit.eq(trigger0.hit)
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]
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#
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# Interrupts
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#===============================================================================
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interrupts = Fragment([
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cpu0.interrupt[interrupt_n("UART")].eq(uart0.irq),
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cpu0.interrupt[interrupt_n("RC5")].eq(rc50.irq),
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cpu0.interrupt[interrupt_n("GPIO")].eq(gpio0.irq)
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])
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#
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# HouseKeeping
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#===============================================================================
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frag = autofragment.from_local() + interrupts
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cst = Constraints(uart0, rc50, gpio0, led0, sw0, spi_master0, hpdmc0)
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frag = autofragment.from_local()
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frag += Fragment(sync=sync,comb=comb)
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cst = Constraints()
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src_verilog, vns = verilog.convert(frag,
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cst.get_ios(),
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name="soc",
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name="de0_nano",
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return_ns=True)
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src_qsf = cst.get_qsf(vns)
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return (src_verilog, src_qsf)
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@ -110,7 +110,7 @@ class Spi2Csr :
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spi_addr.eq(Cat(spi_mosi_dat,spi_addr[:self.a_width-1]))
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).Elif((spi_cnt >= (self.a_width+self.d_width)) & last_b,
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spi_addr.eq(spi_addr+1)
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).Elif((spi_cnt >= self.a_width) & last_b & (spi_cnt[self.a_width-1] == 0),
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).Elif((spi_cnt >= self.a_width) & last_b & (spi_addr[self.a_width-1] == 0),
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spi_addr.eq(spi_addr+1)
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),
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# dat
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