soc/integration: add new soc class prorotype with SoCRegion/SoCBus/SoCCSR/SoCIRQ/SoC
This commit is contained in:
Florent Kermarrec
parent
9b11e9192d
commit
6baa07a69b
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@ -0,0 +1,559 @@
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#!/usr/bin/env python3
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import logging
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import time
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import datetime
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from migen import *
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from litex.soc.interconnect import wishbone
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# TODO:
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# - replace raise with exit on logging error.
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# - use common module for SoCCSR/SoCIRQ.
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# - add configurable CSR paging.
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# - manage IO/Linker regions.
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logging.basicConfig(level=logging.INFO)
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# Helpers ------------------------------------------------------------------------------------------
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def colorer(s, color="bright"):
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header = {
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"bright": "\x1b[1m",
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"green": "\x1b[32m",
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"cyan": "\x1b[36m",
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"red": "\x1b[31m",
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"yellow": "\x1b[33m",
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"underline": "\x1b[4m"}[color]
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trailer = "\x1b[0m"
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return header + str(s) + trailer
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def buildtime(with_time=True):
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fmt = "%Y-%m-%d %H:%M:%S" if with_time else "%Y-%m-%d"
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return datetime.datetime.fromtimestamp(time.time()).strftime("%Y-%m-%d %H:%M:%S")
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# SoCRegion ----------------------------------------------------------------------------------------
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class SoCRegion:
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def __init__(self, origin=None, size=None, cached=True):
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self.logger = logging.getLogger("SoCRegion")
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self.origin = origin
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self.size = size
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self.cached = cached
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def decoder(self):
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origin = self.origin
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size = self.size
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origin &= ~0x80000000
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size = 2**log2_int(size, False)
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if (origin & (size - 1)) != 0:
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self.logger.error("Origin needs to be aligned on size:")
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self.logger.error(self)
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raise
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origin >>= 2 # bytes to words aligned
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size >>= 2 # bytes to words aligned
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return lambda a: (a[log2_int(size):-1] == (origin >> log2_int(size)))
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def __str__(self):
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r = ""
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if self.origin is not None:
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r += "Origin: {}, ".format(colorer("0x{:08x}".format(self.origin)))
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if self.size is not None:
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r += "Size: {}, ".format(colorer("0x{:08x}".format(self.size)))
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r += "Cached: {}".format(colorer(self.cached))
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return r
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class SoCLinkerRegion(SoCRegion):
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pass
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# SoCBus -------------------------------------------------------------------------------------------
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class SoCBus:
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supported_standard = ["wishbone"]
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supported_data_width = [32, 64]
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supported_address_width = [32]
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# Creation -------------------------------------------------------------------------------------
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def __init__(self, standard, data_width=32, address_width=32, timeout=1e6, reserved_regions={}):
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self.logger = logging.getLogger("SoCBus")
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self.logger.info(colorer("Creating new Bus Handler...", color="cyan"))
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# Check Standard
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if standard not in self.supported_standard:
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self.logger.error("Unsupported Standard: {} supporteds: {:s}".format(
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colorer(standard, color="red"),
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colorer(", ".join(self.supported_standard), color="green")))
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raise
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# Check Data Width
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if data_width not in self.supported_data_width:
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self.logger.error("Unsupported Data_Width: {} supporteds: {:s}".format(
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colorer(data_width, color="red"),
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colorer(", ".join(str(x) for x in self.supported_data_width), color="green")))
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raise
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# Check Address Width
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if address_width not in self.supported_address_width:
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self.logger.error("Unsupported Address Width: {} supporteds: {:s}".format(
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colorer(data_width, color="red"),
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colorer(", ".join(str(x) for x in self.supported_address_width), color="green")))
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raise
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# Create Bus
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self.standard = standard
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self.data_width = data_width
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self.address_width = address_width
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self.masters = {}
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self.slaves = {}
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self.regions = {}
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self.timeout = timeout
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self.logger.info("{}-bit {} Bus, {}GiB Address Space.".format(
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colorer(data_width), colorer(standard), colorer(2**address_width/2**30)))
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# Adding reserved regions
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self.logger.info("Adding {} Regions...".format(colorer("reserved")))
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for name, region in reserved_regions.items():
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if isinstance(region, int):
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region = SoCRegion(origin=region, size=0x1000000)
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self.add_region(name, region)
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self.logger.info(colorer("Bus Handler created.", color="cyan"))
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# Add/Allog/Check Regions ----------------------------------------------------------------------
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def add_region(self, name, region):
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allocated = False
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# Check if SoCLinkerRegion
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if isinstance(region, SoCLinkerRegion):
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self.logger.info("FIXME: SoCLinkerRegion")
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# Check if SoCRegion
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elif isinstance(region, SoCRegion):
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# If no origin specified, allocate region.
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if region.origin is None:
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allocated = True
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region = self.alloc_region(region.size, region.cached)
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self.regions[name] = region
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# Else add region and check for overlaps.
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else:
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self.regions[name] = region
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overlap = self.check_region(self.regions)
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if overlap is not None:
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self.logger.error("Region overlap between {} and {}:".format(
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colorer(overlap[0], color="red"),
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colorer(overlap[1], color="red")))
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self.logger.error(str(self.regions[overlap[0]]))
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self.logger.error(str(self.regions[overlap[1]]))
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raise
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self.logger.info("{} Region {} {}.".format(
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colorer(name, color="underline"),
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colorer("allocated" if allocated else "added", color="yellow" if allocated else "green"),
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str(region)))
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else:
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self.logger.error("{} is not a supported Region".format(colorer(name, color="red")))
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raise
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def alloc_region(self, size, cached=True):
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self.logger.info("Allocating {} Region of size {}...".format(
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colorer("Cached" if cached else "IO"),
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colorer("0x{:08x}".format(size))))
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# Limit Search Regions
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uncached_regions = {}
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for _, region in self.regions.items():
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if region.cached == False:
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uncached_regions[name] = region
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if cached == False:
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search_regions = uncached_regions
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else:
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search_regions = {"main": SoCRegion(origin=0x00000000, size=2**self.address_width-1)}
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# Iterate on Search_Regions to find a Candidate
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for _, search_region in search_regions.items():
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origin = search_region.origin
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while (origin + size) < (search_region.origin + search_region.size):
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# Create a Candicate.
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candidate = SoCRegion(origin=origin, size=size, cached=cached)
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overlap = False
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# Check Candidate does not overlap with allocated existing regions
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for _, allocated in self.regions.items():
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if self.check_region({"0": allocated, "1": candidate}) is not None:
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origin = allocated.origin + allocated.size
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overlap = True
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break
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if not overlap:
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# If no overlap, the Candidate is selected
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return candidate
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self.logger.error("Not enough Address Space to allocate Region")
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raise
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def check_region(self, regions):
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i = 0
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while i < len(regions):
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n0 = list(regions.keys())[i]
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r0 = regions[n0]
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for n1 in list(regions.keys())[i+1:]:
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r1 = regions[n1]
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if isinstance(r0, SoCLinkerRegion) or isinstance(r1, SoCLinkerRegion):
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continue
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if r0.origin >= (r1.origin + r1.size):
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continue
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if r1.origin >= (r0.origin + r0.size):
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continue
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return (n0, n1)
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i += 1
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return None
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# Add Master/Slave -----------------------------------------------------------------------------
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def add_master(self, name=None, master=None, io_regions={}):
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if name is None:
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name = "master{:d}".format(len(self.masters))
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if name in self.masters.keys():
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self.logger.error("{} already declared as Bus Master:".format(colorer(name, color="red")))
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self.logger.error(self)
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raise
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self.masters[name] = master
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self.logger.info("{} {} as Bus Master.".format(colorer(name, color="underline"), colorer("added", color="green")))
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# FIXME: handle IO regions
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def add_slave(self, name=None, slave=None, region=None):
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no_name = name is None
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no_region = region is None
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if no_name and no_region:
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self.logger.error("Please specify at least {} or {} of Bus Slave".format(
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colorer("name", color="red"),
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colorer("region", color="red")))
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raise
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if no_name:
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name = "slave{:d}".format(len(self.slaves))
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if no_region:
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region = self.regions.get(name, None)
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if region is None:
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self.logger.error("Unable to find Region {}".format(colorer(name, color="red")))
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raise
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else:
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self.add_region(name, region)
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if name in self.slaves.keys():
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self.logger.error("{} already declared as Bus Slave:".format(colorer(name, color="red")))
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self.logger.error(self)
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raise
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self.slaves[name] = slave
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self.logger.info("{} {} as Bus Slave.".format(
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colorer(name, color="underline"),
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colorer("added", color="green")))
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# Str ------------------------------------------------------------------------------------------
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def __str__(self):
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r = "{}-bit {} Bus, {}GiB Address Space.\n".format(
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colorer(self.data_width), colorer(self.standard), colorer(2**self.address_width/2**30))
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r += "Bus Regions: ({})\n".format(len(self.regions.keys())) if len(self.regions.keys()) else ""
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for name, region in self.regions.items():
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r += colorer(name, color="underline") + " "*(20-len(name)) + ": " + str(region) + "\n"
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r += "Bus Masters: ({})\n".format(len(self.masters.keys())) if len(self.masters.keys()) else ""
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for name in self.masters.keys():
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r += "- {}\n".format(colorer(name, color="underline"))
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r += "Bus Slaves: ({})\n".format(len(self.slaves.keys())) if len(self.slaves.keys()) else ""
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for name in self.slaves.keys():
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r += "- {}\n".format(colorer(name, color="underline"))
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r = r[:-1]
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return r
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# SoCCSR ----------------------------------------------------------------------------------------
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class SoCCSR:
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supported_data_width = [8, 32]
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supported_address_width = [14, 15]
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supported_alignment = [32, 64]
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supported_paging = [0x800]
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# Creation -------------------------------------------------------------------------------------
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def __init__(self, data_width=32, address_width=14, alignment=32, paging=0x800, reserved_csrs={}):
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self.logger = logging.getLogger("SoCCSR")
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self.logger.info(colorer("Creating new CSR Handler...", color="cyan"))
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# Check Data Width
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if data_width not in self.supported_data_width:
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self.logger.error("Unsupported data_width: {} supporteds: {:s}".format(
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colorer(data_width, color="red"),
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colorer(", ".join(str(x) for x in self.supported_data_width)), color="green"))
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raise
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# Check Address Width
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if address_width not in self.supported_address_width:
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self.logger.error("Unsupported address_width: {} supporteds: {:s}".format(
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colorer(address_width, color="red"),
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colorer(", ".join(str(x) for x in self.supported_address_width), color="green")))
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raise
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# Check Alignment
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if alignment not in self.supported_alignment:
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self.logger.error("Unsupported alignment: {} supporteds: {:s}".format(
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colorer(alignment, color="red"),
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colorer(", ".join(str(x) for x in self.supported_alignment), color="green")))
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raise
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# Check Paging
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if paging not in self.supported_paging:
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self.logger.error("Unsupported paging: {} supporteds: {:s}".format(
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colorer(paging, color="red"),
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colorer(", ".join(str(x) for x in self.supported_paging), color="green")))
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raise
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# Create CSR Handler
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self.data_width = data_width
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self.address_width = address_width
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self.alignment = alignment
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self.paging = paging
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self.csrs = {}
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self.n_csrs = 4*2**address_width//paging # FIXME
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self.logger.info("{}-bit CSR Bus, {}KiB Address Space, {}B Paging (Up to {} Locations).\n".format(
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colorer(self.data_width),
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colorer(2**self.address_width/2**10),
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colorer(self.paging),
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self.n_csrs))
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# Adding reserved CSRs
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self.logger.info("Adding {} CSRs...".format(colorer("reserved")))
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for name, n in reserved_csrs.items():
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self.add(name, n)
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self.logger.info(colorer("CSR Bus Handler created.", color="cyan"))
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# Add ------------------------------------------------------------------------------------------
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def add(self, name, n=None):
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allocated = False
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if name in self.csrs.keys():
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self.logger.error("{} CSR name already used.".format(colorer(name, "red")))
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self.logger.error(self)
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raise
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if n in self.csrs.values():
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self.logger.error("{} CSR Location already used.".format(colorer(n, "red")))
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self.logger.error(self)
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raise
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if n is None:
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allocated = True
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n = self.alloc(name)
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else:
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if n < 0:
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self.logger.error("{} CSR Location should be positive.".format(
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colorer(n, color="red")))
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raise
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if n > self.n_csrs:
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self.logger.error("{} CSR Location too high (Up to {}).".format(
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colorer(n, color="red"),
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colorer(self.n_csrs, color="green")))
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raise
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self.csrs[name] = n
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self.logger.info("{} CSR {} at Location {}.".format(
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colorer(name, color="underline"),
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colorer("allocated" if allocated else "added", color="yellow" if allocated else "green"),
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colorer(n)))
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# Alloc ----------------------------------------------------------------------------------------
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def alloc(self, name):
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for n in range(self.data_width//8*2**self.address_width//self.paging):
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if n not in self.csrs.values():
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return n
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self.logger.error("Not enough CSR Locations.")
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self.logger.error(self)
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raise
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# Str ------------------------------------------------------------------------------------------
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def __str__(self):
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r = "{}-bit CSR Bus, {}KiB Address Space, {}B Paging (Up to {} Locations).\n".format(
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colorer(self.data_width),
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colorer(2**self.address_width/2**10),
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colorer(self.paging),
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self.n_csrs)
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r += "CSR Locations: ({})\n".format(len(self.csrs.keys())) if len(self.csrs.keys()) else ""
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for name in self.csrs.keys():
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r += "- {}{}: {}\n".format(colorer(name, color="underline"), " "*(20-len(name)), colorer(self.csrs[name]))
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r = r[:-1]
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return r
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# SoCIRQ -------------------------------------------------------------------------------------------
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class SoCIRQ:
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# Creation -------------------------------------------------------------------------------------
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def __init__(self, n_irqs=32, reserved_irqs={}):
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self.logger = logging.getLogger("SoCIRQ")
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self.logger.info(colorer("Creating new SoC IRQ Handler...", color="cyan"))
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# Check IRQ Number
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if n_irqs > 32:
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self.logger.error("Unsupported IRQs number: {} supporteds: {:s}".format(
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colorer(n, color="red"), colorer("Up to 32", color="green")))
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raise
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# Create IRQ Handler
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self.n_irqs = n_irqs
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self.irqs = {}
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self.logger.info("IRQ Handler (up to {} Locations).".format(colorer(n_irqs)))
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# Adding reserved IRQs
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self.logger.info("Adding {} IRQs...".format(colorer("reserved")))
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for name, n in reserved_irqs.items():
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self.add(name, n)
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self.logger.info(colorer("IRQ Handler created.", color="cyan"))
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# Add ------------------------------------------------------------------------------------------
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def add(self, name, n=None):
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allocated = False
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if name in self.irqs.keys():
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self.logger.error("{} IRQ name already used.".format(colorer(name, "red")))
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self.logger.error(self)
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raise
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if n in self.irqs.values():
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self.logger.error("{} IRQ Location already used.".format(colorer(n, "red")))
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self.logger.error(self)
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raise
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if n is None:
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allocated = True
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n = self.alloc(name)
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else:
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if n < 0:
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self.logger.error("{} IRQ Location should be positive.".format(
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colorer(n, color="red")))
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raise
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if n > self.n_irqs:
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self.logger.error("{} IRQ Location too high (Up to {}).".format(
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colorer(n, color="red"),
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colorer(self.n_csrs, color="green")))
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raise
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self.irqs[name] = n
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self.logger.info("{} IRQ {} at Location {}.".format(
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colorer(name, color="underline"),
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colorer("allocated" if allocated else "added", color="yellow" if allocated else "green"),
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colorer(n)))
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# Alloc ----------------------------------------------------------------------------------------
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def alloc(self, name):
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for n in range(self.n_irqs):
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if n not in self.irqs.values():
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return n
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self.logger.error("Not enough Locations.")
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self.logger.error(self)
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raise
|
||||
|
||||
# Str ------------------------------------------------------------------------------------------
|
||||
def __str__(self):
|
||||
r ="IRQ Handler (up to {} Locations).\n".format(colorer(self.n_irqs))
|
||||
r += "IRQs Locations:\n" if len(self.irqs.keys()) else ""
|
||||
for name in self.irqs.keys():
|
||||
r += "- {}{}: {}\n".format(colorer(name, color="underline"), " "*(20-len(name)), colorer(self.irqs[name]))
|
||||
r = r[:-1]
|
||||
return r
|
||||
|
||||
# SoC ----------------------------------------------------------------------------------------------
|
||||
|
||||
class SoC(Module):
|
||||
def __init__(self,
|
||||
bus_standard = "wishbone",
|
||||
bus_data_width = 32,
|
||||
bus_address_width = 32,
|
||||
bus_timeout = 1e6,
|
||||
bus_reserved_regions = {},
|
||||
|
||||
csr_data_width = 32,
|
||||
csr_address_width = 14,
|
||||
csr_alignment = 32,
|
||||
csr_paging = 0x800,
|
||||
csr_reserved_csrs = {},
|
||||
|
||||
irq_n_irqs = 32,
|
||||
irq_reserved_irqs = {},
|
||||
):
|
||||
|
||||
self.logger = logging.getLogger("SoC")
|
||||
self.logger.info(colorer(" __ _ __ _ __ ", color="bright"))
|
||||
self.logger.info(colorer(" / / (_) /____ | |/_/ ", color="bright"))
|
||||
self.logger.info(colorer(" / /__/ / __/ -_)> < ", color="bright"))
|
||||
self.logger.info(colorer(" /____/_/\\__/\\__/_/|_| ", color="bright"))
|
||||
self.logger.info(colorer(" Build your hardware, easily!", color="bright"))
|
||||
|
||||
self.logger.info(colorer("-"*80, color="bright"))
|
||||
self.logger.info(colorer("Creating new SoC... ({})".format(buildtime()), color="cyan"))
|
||||
self.logger.info(colorer("-"*80, color="bright"))
|
||||
|
||||
# SoC Bus Handler --------------------------------------------------------------------------
|
||||
self.bus = SoCBus(
|
||||
standard = bus_standard,
|
||||
data_width = bus_data_width,
|
||||
address_width = bus_address_width,
|
||||
timeout = bus_timeout,
|
||||
reserved_regions = bus_reserved_regions,
|
||||
)
|
||||
|
||||
# SoC Bus Handler --------------------------------------------------------------------------
|
||||
self.csr = SoCCSR(
|
||||
data_width = csr_data_width,
|
||||
address_width = csr_address_width,
|
||||
alignment = csr_alignment,
|
||||
paging = csr_paging,
|
||||
reserved_csrs = csr_reserved_csrs,
|
||||
)
|
||||
|
||||
# SoC IRQ Handler --------------------------------------------------------------------------
|
||||
self.irq = SoCIRQ(
|
||||
n_irqs = irq_n_irqs,
|
||||
reserved_irqs = irq_reserved_irqs
|
||||
)
|
||||
|
||||
self.logger.info(colorer("-"*80, color="bright"))
|
||||
self.logger.info(colorer("Initial SoC:", color="cyan"))
|
||||
self.logger.info(colorer("-"*80, color="bright"))
|
||||
self.logger.info(self.bus)
|
||||
self.logger.info(self.csr)
|
||||
self.logger.info(self.irq)
|
||||
self.logger.info(colorer("-"*80, color="bright"))
|
||||
|
||||
|
||||
def do_finalize(self):
|
||||
self.logger.info(colorer("-"*80, color="bright"))
|
||||
self.logger.info(colorer("Finalized SoC:", color="cyan"))
|
||||
self.logger.info(colorer("-"*80, color="bright"))
|
||||
self.logger.info(self.bus)
|
||||
self.logger.info(self.csr)
|
||||
self.logger.info(self.irq)
|
||||
self.logger.info(colorer("-"*80, color="bright"))
|
||||
|
||||
# SoC Bus Interconnect ---------------------------------------------------------------------
|
||||
bus_masters = self.bus.masters.values()
|
||||
bus_slaves = [(self.bus.regions[n].decoder(), s) for n, s in self.bus.slaves.items()]
|
||||
if len(bus_masters) and len(bus_slaves):
|
||||
self.submodules.bus_interconnect = wishbone.InterconnectShared(
|
||||
masters = bus_masters,
|
||||
slaves = bus_slaves,
|
||||
register = True,
|
||||
timeout_cycles = self.bus.timeout)
|
||||
|
||||
#exit()
|
||||
|
||||
# Test (FIXME: move to litex/text and improve) -----------------------------------------------------
|
||||
|
||||
if __name__ == "__main__":
|
||||
bus = SoCBus("wishbone", reserved_regions={
|
||||
"rom": SoCRegion(origin=0x00000100, size=1024),
|
||||
"ram": SoCRegion(size=512),
|
||||
}
|
||||
)
|
||||
bus.add_master("cpu", None)
|
||||
bus.add_slave("rom", None, SoCRegion(size=1024))
|
||||
bus.add_slave("ram", None, SoCRegion(size=1024))
|
||||
|
||||
|
||||
csr = SoCCSR(reserved_csrs={"ctrl": 0, "uart": 1})
|
||||
csr.add("csr0")
|
||||
csr.add("csr1", 0)
|
||||
#csr.add("csr2", 46)
|
||||
csr.add("csr3", -1)
|
||||
print(bus)
|
||||
print(csr)
|
||||
|
||||
irq = SoCIRQ(reserved_irqs={"uart": 1})
|
||||
|
||||
soc = SoC()
|
||||
Loading…
Reference in New Issue