setup: add vexriscv_debug to list of entrypoints

Add the vexriscv_debug program to the list of scripts created when
installing this module.  This program is a simple bridge that allows
openocd to talk to the vexriscv core so it can be debugged.

Signed-off-by: Sean Cross <sean@xobs.io>

litex/soc/tools/vexriscv_debug.py

@@ -44,9 +44,6 @@ class VexRiscvDebugBridge():
         parser.add_argument("--csr", default="test/csr.csv", help="csr mapping file")
         self.args = parser.parse_args()
 
-    def temperature(self):
-        return self.rc.read(self.rc.regs.xadc_temperature.addr) * 503.975 / 4096 - 273.15
-
     def accept(self):
         if hasattr(self, "debugger"):
             return
@@ -85,7 +82,6 @@ class VexRiscvDebugBridge():
 def main():
     vrvb = VexRiscvDebugBridge()
     vrvb.open()
-    print("FPGA Temperature: {} C".format(vrvb.temperature()))
 
     while True:
         vrvb.accept()

setup.py

@@ -38,7 +38,8 @@ setup(
         "console_scripts": [
             "litex_term=litex.soc.tools.litex_term:main",
             "mkmscimg=litex.soc.tools.mkmscimg:main",
-            "litex_server=litex.soc.tools.remote.litex_server:main"
+            "litex_server=litex.soc.tools.remote.litex_server:main",
+            "vexriscv_bridge=litex.soc.tools.vexriscv_debug:main"
         ],
     },
 )