mac: fix gap inserter/checker
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@ -12,7 +12,8 @@ class LiteEthMACCore(Module, AutoCSR):
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# Interpacket gap
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tx_gap_inserter = gap.LiteEthMACGap(phy.dw)
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rx_gap_checker = gap.LiteEthMACGap(phy.dw, ack_on_gap=True)
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self.submodules += tx_gap_inserter, rx_gap_checker
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self.submodules += RenameClockDomains(tx_gap_inserter, "eth_tx")
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self.submodules += RenameClockDomains(rx_gap_checker, "eth_rx")
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tx_pipeline += [tx_gap_inserter]
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rx_pipeline += [rx_gap_checker]
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@ -57,8 +58,8 @@ class LiteEthMACCore(Module, AutoCSR):
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rx_pipeline += [rx_converter]
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# Cross Domain Crossing
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tx_cdc = AsyncFIFO(eth_phy_description(dw), 8)
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rx_cdc = AsyncFIFO(eth_phy_description(dw), 8)
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tx_cdc = AsyncFIFO(eth_phy_description(dw), 64)
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rx_cdc = AsyncFIFO(eth_phy_description(dw), 64)
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self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
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self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
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