cpu/serv: switch to pythondata package instead of local git clone.
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@ -6,6 +6,7 @@ import os
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from migen import *
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from migen import *
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from litex import get_data_mod
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.cpu import CPU
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from litex.soc.cores.cpu import CPU
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@ -80,11 +81,9 @@ class SERV(CPU):
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@staticmethod
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@staticmethod
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def add_sources(platform):
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def add_sources(platform):
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# FIXME: add SERV as submodule
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vdir = get_data_mod("cpu", "serv").data_location
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os.system("git clone https://github.com/olofk/serv")
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platform.add_source_dir(os.path.join(vdir, "rtl"))
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vdir = os.path.join("serv", "rtl")
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platform.add_verilog_include_path(os.path.join(vdir, "rtl"))
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platform.add_source_dir(vdir)
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platform.add_verilog_include_path(vdir)
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def do_finalize(self):
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def do_finalize(self):
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assert hasattr(self, "reset_address")
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assert hasattr(self, "reset_address")
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@ -42,6 +42,7 @@ repos = [
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("pythondata-cpu-lm32", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-lm32", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-mor1kx", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-mor1kx", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-picorv32", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-picorv32", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-serv", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-vexriscv", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-vexriscv", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-rocket", ("https://github.com/litex-hub/", False, True)),
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("pythondata-cpu-rocket", ("https://github.com/litex-hub/", False, True)),
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]
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]
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