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soc/integration/soc: add_sdram, remove litedram_wb and converter: let LiteDRAMWishbone2Native dealing with addr/data width

This commit is contained in:
Gwenhael Goavec-Merou 2023-12-12 12:05:47 +01:00
parent 08ff003178
commit 6d34b8ed87
1 changed files with 2 additions and 5 deletions
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7
litex/soc/integration/soc.py
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@ -1710,15 +1710,12 @@ class LiteXSoC(SoC):
if l2_cache_full_memory_we: if l2_cache_full_memory_we:
l2_cache = FullMemoryWE()(l2_cache) l2_cache = FullMemoryWE()(l2_cache)
self.l2_cache = l2_cache self.l2_cache = l2_cache
litedram_wb = self.l2_cache.slave wb_sdram = self.l2_cache.slave
self.add_config("L2_SIZE", l2_cache_size) self.add_config("L2_SIZE", l2_cache_size)
else:
litedram_wb = wishbone.Interface(data_width=port.data_width, address_width=32, addressing="word")
self.submodules += wishbone.Converter(wb_sdram, litedram_wb)
# Wishbone Slave <--> LiteDRAM bridge. # Wishbone Slave <--> LiteDRAM bridge.
self.wishbone_bridge = LiteDRAMWishbone2Native( self.wishbone_bridge = LiteDRAMWishbone2Native(
wishbone = litedram_wb, wishbone = wb_sdram,
port = port, port = port,
base_address = self.bus.regions["main_ram"].origin base_address = self.bus.regions["main_ram"].origin
) )